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    • 1. 发明授权
    • Synchronizing signal generation circuit
    • 同步信号发生电路
    • US5686968A
    • 1997-11-11
    • US637605
    • 1996-04-25
    • Mikio UjiieHisato Kokubo
    • Mikio UjiieHisato Kokubo
    • G09G5/00G09G5/18H04N5/06
    • H04N5/06
    • The present invention relates to a synchronizing signal generation circuit equipped with a PLL circuit. A pulse signal having a time constant that is broader than the clock width of a horizontal synchronizing signal included within synchronizing signals and that moreover contains steady-state phase error of the PLL circuit is generated and inputted to a phase comparison inhibiting circuit by way of a signal conversion circuit. The logic level of the pulse signal is then varied for the active interval and the inactive interval of the vertical synchronizing signal, phase comparison of the horizontal synchronizing signal and the reproduced horizontal synchronizing signal being inhibited during the active interval. The reproduced horizontal synchronizing signal is generated based on the output of two frequency dividers.
    • 本发明涉及一种配备有PLL电路的同步信号发生电路。 具有比包括在同步信号内的水平同步信号的时钟宽度更宽的时间常数并且还包含PLL电路的稳态相位误差的脉冲信号被产生并通过以下方式输入到相位比较禁止电路 信号转换电路。 然后脉冲信号的逻辑电平在有源间隔和垂直同步信号的无效间隔,水平同步信号和再生水平同步信号的相位比较在有效间隔期间被禁止时变化。 基于两个分频器的输出产生再现的水平同步信号。