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    • 7. 发明申请
    • SEMICONDUCTOR MEMORY AND SYSTEM
    • 半导体存储器和系统
    • US20120087172A1
    • 2012-04-12
    • US13240492
    • 2011-09-22
    • Masaki Aoki
    • Masaki Aoki
    • G11C11/00
    • G11C13/003G11C11/16G11C11/1659G11C11/1673G11C11/1675G11C13/0004G11C13/0007G11C13/004G11C29/021G11C29/028G11C2213/79
    • A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.
    • 半导体存储器包括:实际存储单元,包括通过连接节点串联连接在第一电压线和第二电压线之间的选择晶体管和电阻可变元件,具有连接到连接节点的栅极的实际放大晶体管, 连接到参考电压线的源极和连接到实际读取线的漏极,以及读出放大器,用于通过接收由连接中产生的电压而变化的真实读取线的电压来确定保持在实际存储单元中的逻辑 所述选择晶体管在所述栅极处接收读取控制电压,所述选择晶体管在所述栅极处接收读取控制电压。
    • 9. 发明授权
    • Magnetic memory device and method for reading the same
    • 磁记忆装置及其读取方法
    • US07489577B2
    • 2009-02-10
    • US11808967
    • 2007-06-14
    • Yoshihiro SatoMasaki Aoki
    • Yoshihiro SatoMasaki Aoki
    • G11C7/02
    • G11C11/16
    • A magnetic memory device comprises a plurality of bit lines BL; memory cells MC disposed at the respective plurality of bit lines, and each including a magnetoresistive effect element MTJ whose resistance value is changed with changes of magnetization direction, and a select transistor Tr connected to the magnetoresistive effect element MTJ, the magnetoresistive effect element MC having one terminal connected to the bit line BL and the other terminal connected to a first signal line GND via the select transistor; dummy cells DC disposed at the respective plurality of bit lines BL, and each including a resistance element R of a constant resistance value, the resistance element having one terminal connected to the bit line BL and the other terminal connected to a second signal line SIGD; and a voltage sense amplifier SA connected to the plurality of bit lines BL.
    • 磁存储器件包括多个位线BL; 存储单元MC设置在相应的多个位线处,并且每个存储单元MC包括电阻值随着磁化方向的变化而变化的磁阻效应元件MTJ以及连接到磁阻效应元件MTJ的选择晶体管Tr,磁阻效应元件MC具有 一个端子连接到位线BL,另一个端子经由选择晶体管连接到第一信号线GND; 设置在各个位线BL上的虚设单元DC,并且每个都包括具有恒定电阻值的电阻元件R,该电阻元件具有连接到位线BL的一个端子,而另一个端子连接到第二信号线SIGD; 以及连接到多个位线BL的电压检测放大器SA。