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1. 发明申请

US20050142740A1 Method and resulting structure for fabricating dram cell structure using oxide line spacer 有权
公开(公告)号：US20050142740A1
公开(公告)日：2005-06-30
申请号：US10773799
申请日：2004-02-06
申请人： Mieno Fumitake , Bong Jae Lee , Guoqing Chen
发明人： Mieno Fumitake , Bong Jae Lee , Guoqing Chen
IPC分类号： H01L21/316 , H01L21/336 , H01L21/44 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A method for forming bit line and storage node contacts for a dynamic random access device, e.g., DRAM. Other devices (e.g., Flash, EEPROM) may also be included. The method includes providing a substrate, which has a bit line region and a capacitor contact region. The method also includes forming at least a first gate structure and a second gate structure overlying the substrate. The first gate structure and the second gate structure include an overlying cap. The method also includes forming a conformal dielectric layer overlying the first gate structure, the second gate structure, the bit line region, and the capacitor contact region. The method includes forming an interlayer dielectric material overlying the conformal dielectric layer and planarizing the interlayer dielectric material. The method includes forming a masking layer overlying the planarized interlayer dielectric material and exposing a continuous common region within a portion of the planarized interlayer dielectric material overlying a portion of the first gate structure, a portion of the second gate structure, a portion of the bit line region, and a portion of the capacitor contact region. A first etching process is performed to remove the exposed portion of the planarized interlayer dielectric layer. A second etching process is performed to remove a portion of the conformal dielectric layer on the bit line region and to remove a portion of the conformal dielectric layer on the capacitor contact region while using other portions of the conformal layer as a mask to prevent a portion of the first gate structure and a portion of the second gate structure from being exposed. The method deposits a polysilicon fill material within the continuous common region and overlying the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to cover portions of the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to a predetermined thickness. The method includes planarizing the polysilicon fill material to reduce the predetermined thickness and to simultaneously reduce a thickness of a portion of the interlayer dielectric material

2. 发明授权

US06967161B2 Method and resulting structure for fabricating DRAM cell structure using oxide line spacer 有权
公开(公告)号：US06967161B2
公开(公告)日：2005-11-22
申请号：US10773799
申请日：2004-02-06
申请人： Mieno Fumitake , Bong Jae Lee , Guoqing Chen
发明人： Mieno Fumitake , Bong Jae Lee , Guoqing Chen
IPC分类号： H01L21/316 , H01L21/336 , H01L21/44 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A method for forming bit line and storage node contacts for a dynamic random access device, e.g., DRAM. Other devices (e.g., Flash, EEPROM) may also be included. The method includes providing a substrate, which has a bit line region and a capacitor contact region. The method also includes forming at least a first gate structure and a second gate structure overlying the substrate. The first gate structure and the second gate structure include an overlying cap. The method also includes forming a conformal dielectric layer overlying the first gate structure, the second gate structure, the bit line region, and the capacitor contact region. The method includes forming an interlayer dielectric material overlying the conformal dielectric layer and planarizing the interlayer dielectric material. The method includes forming a masking layer overlying the planarized interlayer dielectric material and exposing a continuous common region within a portion of the planarized interlayer dielectric material overlying a portion of the first gate structure, a portion of the second gate structure, a portion of the bit line region, and a portion of the capacitor contact region. A first etching process is performed to remove the exposed portion of the planarized interlayer dielectric layer. A second etching process is performed to remove a portion of the conformal dielectric layer on the bit line region and to remove a portion of the conformal dielectric layer on the capacitor contact region while using other portions of the conformal layer as a mask to prevent a portion of the first gate structure and a portion of the second gate structure from being exposed. The method deposits a polysilicon fill material within the continuous common region and overlying the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to cover portions of the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to a predetermined thickness. The method includes planarizing the polysilicon fill material to reduce the predetermined thickness and to simultaneously reduce a thickness of a portion of the interlayer dielectric material.

3. 发明授权

US08716080B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08716080B2
公开(公告)日：2014-05-06
申请号：US13481803
申请日：2012-05-26
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/845 , H01L27/1211 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices.
摘要翻译：半导体器件被描述为包括具有由第一半导体材料形成的层的第一鳍片和由第二半导体材料形成的第二鳍片。第一和第二半导体材料是不同的。第二半导体材料可以具有大于第一半导体材料的P型载流子的迁移率的P型载流子的迁移率。第二鳍包括由第二半导体材料形成的层下面的第一半导体材料形成的层。半导体器件还包括设置在第一和第二鳍片上的硬掩模层和设置在第一鳍片和第二鳍片下方的绝缘体层。第一和第二半导体材料分别包括硅和锗。第一和第二鳍用于形成相应的N沟道和P沟道半导体器件。

4. 发明授权

US08569757B2 Semiconductor device with amorphous silicon MAS memory cell structure and manufacturing method thereof 有权
标题翻译：具有非晶硅MAS存储单元结构的半导体器件及其制造方法
公开(公告)号：US08569757B2
公开(公告)日：2013-10-29
申请号：US13333994
申请日：2011-12-21
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L29/04
CPC分类号： H01L29/792 , H01L27/11568 , H01L27/12 , H01L29/8616
摘要： A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.
摘要翻译：具有非晶硅（a-Si）金属 - 氧化铝半导体（MAS）存储单元结构的半导体器件。该器件包括衬底，覆盖在衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域，其中n型a-Si的共面表面和电介质层。另外，器件包括p-i-n a-Si二极管结。该器件还包括在a-Si p-i-n二极管结上的氧化铝电荷俘获层和覆盖氧化铝层的金属控制栅极。提供了一种用于制造a-Si MAS存储单元结构并且可以重复三维地集成结构的方法。

5. 发明授权

US08546224B2 Method for manufacturing twin bit structure cell with aluminum oxide layer 有权
标题翻译：具有氧化铝层的双位结构单元的制造方法
公开(公告)号：US08546224B2
公开(公告)日：2013-10-01
申请号：US12965808
申请日：2010-12-10
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L21/28282 , H01L21/28114 , H01L29/66833 , H01L29/7923
摘要： A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure.
摘要翻译：制造具有氧化铝材料的双位单元结构的方法包括形成覆盖在半导体衬底上的栅极介电层和覆盖栅极电介质层的多晶硅栅极结构。在多晶硅栅极结构下面的栅极电介质层的每一侧形成底切区域。此后，进行氧化处理以在多晶硅栅极结构的外围表面上形成第一氧化硅层，并在半导体衬底的暴露表面上形成第二氧化硅层。然后，在包括底切区域和栅极介电层的第一和第二氧化硅层上沉积氧化铝材料。选择性地蚀刻氧化铝材料以在底切区域的一部分中形成插入区域。形成侧壁间隔物以隔离和保护暴露的氧化铝材料和多晶硅栅极结构。

6. 发明申请

US20130134488A1 Semiconductor Device and Manufacturing Method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130134488A1
公开(公告)日：2013-05-30
申请号：US13552446
申请日：2012-07-18
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/098 , H01L21/26586 , H01L21/823821 , H01L27/0924 , H01L29/0657 , H01L29/66901 , H01L29/785 , H01L29/808
摘要： A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.
摘要翻译：提供了一种半导体器件及其制造方法。翅片半导体器件包括形成在衬底上的翅片和形成在衬底上并围绕翅片的绝缘材料层。翅片具有半导体层，该半导体层具有源极区部分和漏极区域部分。翅片包括第一通道控制区域，第二通道控制区域和两个通道控制区域之间的通道区域，它们都位于源极区域部分和漏极区域部分之间。两个通道控制区域可以具有与通道区域不同的导电类型。

7. 发明授权

US08975642B2 Transistor device and fabrication method 有权
标题翻译：晶体管器件及其制造方法
公开(公告)号：US08975642B2
公开(公告)日：2015-03-10
申请号：US13686163
申请日：2012-11-27
申请人： Neil Zhao , Mieno Fumitake
发明人： Neil Zhao , Mieno Fumitake
IPC分类号： H01L29/15 , H01L29/78 , H01L29/66 , H01L29/16 , H01L29/267 , H01L29/10 , H01L29/161 , H01L29/165 , H01L21/265
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26566 , H01L29/1054 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/267 , H01L29/66431 , H01L29/665 , H01L29/66575 , Y10S438/931
摘要： Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
摘要翻译：各种实施例提供晶体管器件和制造方法。具有改善的载流子迁移率的示例性晶体管器件可以通过首先在半导体衬底上形成约束层以将从半导体衬底扩散的杂质离子限制到限制层来形成。可以在约束层上形成外延硅层，随后在外延硅层上形成栅极结构。外延硅层的一部分可以用作固有沟道区。源极区域和漏极区域可以形成在每个外延硅层，约束层和半导体衬底的部分中。

8. 发明授权

US08114732B2 Method for manufacturing twin bit structure cell with Al2O3/nano-crystalline Si layer 有权
标题翻译：用Al2O3 /纳米晶硅层制造双位结构电池的方法
公开(公告)号：US08114732B2
公开(公告)日：2012-02-14
申请号：US12704502
申请日：2010-02-11
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L21/336 , H01L21/461 , H01L21/8242
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7887
摘要： A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure.
摘要翻译：一种用于形成非易失性存储器结构的方法和系统。该方法包括提供半导体衬底并形成覆盖在半导体衬底的表面区域上的栅极电介质层。形成覆盖栅极电介质层的多晶硅栅极结构。该方法使多晶硅栅极结构进入氧化环境，以形成覆盖多晶硅栅极结构的第一氧化硅层和在多晶硅栅极结构下方形成底切区域。在填充底切区域的多晶硅栅极结构之上形成氧化铝材料。在具体实施方案中，氧化铝材料具有夹在第一氧化铝层和第二氧化铝层之间的纳米晶硅材料。对氧化铝材料进行选择性蚀刻处理，同时将氧化铝材料保持在切削区域的一部分中的插入区域中。该方法形成覆盖多晶硅栅极结构的侧面区域的侧壁结构。

9. 发明申请

US20110204363A1 AMORPHOUS SILICON MONOS OR MAS MEMORY CELL STRUCTURE WITH OTP FUNCTION 有权
标题翻译：具有OTP功能的非晶硅单体或MAS记忆体细胞结构
公开(公告)号：US20110204363A1
公开(公告)日：2011-08-25
申请号：US13013229
申请日：2011-01-25
申请人： Mieno Fumitake
发明人： Mieno Fumitake
IPC分类号： H01L29/772
CPC分类号： H01L27/11206 , H01L27/112
摘要： A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.
摘要翻译：具有一次可编程（OTP）功能的具有非晶硅（a-Si）金属氧化物 - 氮化物 - 氧化物 - 硅（MONOS）或金属 - 氧化铝 - 硅（MAS）存储单元结构的半导体器件。该器件包括衬底，覆盖衬底的第一电介质层和嵌入在第一介电层中的一个或多个源极或漏极区域，其具有n型a-Si的共面表面和第一介电层。另外，器件包括p-i-n a-Si二极管结。该器件还包括在a-Si p-i-n二极管结上的第二介质层和覆盖第二介电层的金属控制栅极。可选地，具有OTP功能的器件包括在n型a-Si层和金属控制栅极之间形成的导电路径。提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。

10. 发明授权

US07989363B2 Method for rapid thermal treatment using high energy electromagnetic radiation of a semiconductor substrate for formation of dielectric films 有权
标题翻译：使用用于形成介电膜的半导体衬底的高能电磁辐射进行快速热处理的方法
公开(公告)号：US07989363B2
公开(公告)日：2011-08-02
申请号：US12259095
申请日：2008-10-27
申请人： David Gao , Mieno Fumitake
发明人： David Gao , Mieno Fumitake
IPC分类号： H01L21/31
CPC分类号： H01L21/31654 , H01L21/02233 , H01L21/268 , H01L21/2686 , H01L21/28211 , H01L21/28282
摘要： A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections. In a specific embodiment, the oxide layer is a gate oxide layer.
摘要翻译：一种制造半导体器件的方法，例如SONOS电池。该方法包括提供具有自然氧化物层的具有表面区域的半导体衬底（例如，硅晶片，绝缘体上硅）。该方法包括将表面区域处理为湿清洗工艺以从表面区域去除自然氧化物层。在一个具体实施方案中，该方法包括使表面区域承受含氧环境，并使表面区域经受波长为约300至约800纳米的高能电磁辐射，持续时间小于10毫秒至将表面区域的温度增加到大于1000摄氏度。在一个具体实施方案中，该方法导致形成厚度小于10埃的氧化物层。在优选实施例中，氧化物层基本上没有针孔和其它缺陷。在具体实施方案中，氧化物层是栅极氧化物层。

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