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1. 发明申请

US20220336485A1 MICROELECTRONIC DEVICES INCLUDING FILLED SLITS AND MEMORY CELL PILLARS, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS 有权
公开(公告)号：US20220336485A1
公开(公告)日：2022-10-20
申请号：US17233158
申请日：2021-04-16
申请人： Micron Technology, Inc.
发明人： Collin Howder , Justin D. Shepherdson , Chet E. Carter
IPC分类号： H01L27/11578 , H01L27/11575 , H01L25/065
摘要： A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

2. 发明授权

US11411015B2 Memory arrays and methods used in forming a memory array 有权
公开(公告)号：US11411015B2
公开(公告)日：2022-08-09
申请号：US17151344
申请日：2021-01-18
申请人： Micron Technology, Inc.
发明人： Collin Howder , Chet E. Carter
IPC分类号： H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/11565 , H01L21/311 , H01L21/3213
摘要： A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

3. 发明申请

US20220231046A1 Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells 有权
公开(公告)号：US20220231046A1
公开(公告)日：2022-07-21
申请号：US17714924
申请日：2022-04-06
申请人： Micron Technology, Inc.
发明人： Collin Howder , Chet E. Carter
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11556 , H01L27/11524 , H01L21/822
摘要： A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

4. 发明授权

US11069598B2 Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs) 有权
公开(公告)号：US11069598B2
公开(公告)日：2021-07-20
申请号：US16444634
申请日：2019-06-18
申请人： Micron Technology, Inc.
发明人： Indra V. Chary , Chet E. Carter , Anilkumar Chandolu , Justin B. Dorhout , Jun Fang , Matthew J. King , Brett D. Lowe , Matthew Park , Justin D. Shepherdson
IPC分类号： H01L23/48 , H01L27/11582 , H01L27/11565 , H01L21/311 , H01L21/033 , H01L21/768 , H01L21/28 , H01L27/11556 , H01L27/11519
摘要： A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

5. 发明申请

US20210143167A1 Memory Arrays And Methods Used In Forming A Memory Array 有权
公开(公告)号：US20210143167A1
公开(公告)日：2021-05-13
申请号：US17151344
申请日：2021-01-18
申请人： Micron Technology, Inc.
发明人： Collin Howder , Chet E. Carter
IPC分类号： H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/11565
摘要： A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.

6. 发明授权

US10263007B2 Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor 有权
公开(公告)号：US10263007B2
公开(公告)日：2019-04-16
申请号：US16002129
申请日：2018-06-07
申请人： Micron Technology, Inc.
发明人： Justin B. Dorhout , Kunal R. Parekh , Matthew Park , Joseph Neil Greeley , Chet E. Carter , Martin C. Roberts , Indra V. Chary , Vinayak Shamanna , Ryan Meyer , Paolo Tessariol
IPC分类号： H01L21/336 , H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L27/11582 , H01L27/11573
摘要： An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

7. 发明申请

US20190043890A1 Integrated Structures Including Material Containing Silicon, Nitrogen, and at Least One of Carbon, Oxygen, Boron and Phosphorus 审中-公开
公开(公告)号：US20190043890A1
公开(公告)日：2019-02-07
申请号：US16158039
申请日：2018-10-11
申请人： Micron Technology, Inc.
发明人： Justin B. Dorhout , Fei Wang , Chet E. Carter , Ian Laboriante , John D. Hopkins , Kunal Shrotri , Ryan Meyer , Vinayak Shamanna , Kunal R. Parekh , Martin C. Roberts , Matthew Park
IPC分类号： H01L27/11582 , H01L23/528 , H01L23/532 , H01L27/1157
CPC分类号： H01L27/11582 , H01L23/528 , H01L23/53257 , H01L27/1157
摘要： Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

8. 发明授权

US10157933B2 Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus 有权
公开(公告)号：US10157933B2
公开(公告)日：2018-12-18
申请号：US15133119
申请日：2016-04-19
申请人： Micron Technology, Inc.
发明人： Justin B. Dorhout , Fei Wang , Chet E. Carter , Ian Laboriante , John D. Hopkins , Kunal Shrotri , Ryan Meyer , Vinayak Shamanna , Kunal R. Parekh , Martin C. Roberts , Matthew Park
IPC分类号： H01L29/792 , H01L27/11582 , H01L23/528 , H01L23/532
摘要： Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

9. 发明申请

US20180047739A1 Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor And Arrays Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor 有权
公开(公告)号：US20180047739A1
公开(公告)日：2018-02-15
申请号：US15231950
申请日：2016-08-09
申请人： Micron Technology, Inc.
发明人： Justin B. Dorhout , Kunal R. Parekh , Matthew Park , Joseph Neil Greeley , Chet E. Carter , Martin C. Roberts , Indra V. Chary , Vinayak Shamanna , Ryan Meyer , Paolo Tessariol
IPC分类号： H01L27/115
CPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L27/11573 , H01L27/11582
摘要： An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.

10. 发明申请

US20140070419A1 Platinum-Containing Constructions, and Methods of Forming Platinum-Containing Constructions 有权
标题翻译：含铂的结构和形成含铂结构的方法
公开(公告)号：US20140070419A1
公开(公告)日：2014-03-13
申请号：US14080629
申请日：2013-11-14
申请人： Micron Technology, Inc.
发明人： Andrey V. Zagrebelny , Chet E. Carter , Andrew D. Carswell
IPC分类号： H01L29/45 , H01L21/283
CPC分类号： H01L29/45 , H01L21/283 , H01L21/3212 , H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L23/53242 , H01L23/53295 , H01L45/16 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide. Chemical-mechanical polishing is utilized to form a planarized surface extending across the platinum-containing material and the metal oxide.
摘要翻译：一些实施方案包括具有含铂结构的构造。在一些实施方案中，所述结构可以具有穿过含铂结构并穿过金属氧化物的平坦化表面。在一些实施方案中，所述构造可以具有穿过含铂结构的平坦化表面，穿过保持含铂结构的第一材料，以及沿着含铂结构的侧壁穿过金属氧化物衬垫并且直接在含铂的结构之间结构和第一种材料。一些实施方案包括形成含铂结构的方法。在一些实施例中，跨越导电结构形成第一材料，并且跨越第一材料形成金属氧化物。开口形成为延伸穿过金属氧化物和第一材料到导电结构。在开口内和金属氧化物上形成含铂材料。利用化学机械抛光来形成延伸穿过含铂材料和金属氧化物的平坦化表面。

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