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1. 发明申请

US20210265499A1 DEVICES AND SYSTEMS WITH STRING DRIVERS INCLUDING HIGH BAND GAP MATERIAL AND METHODS OF FORMATION 有权
公开(公告)号：US20210265499A1
公开(公告)日：2021-08-26
申请号：US17316943
申请日：2021-05-11
申请人： Micron Technology, Inc.
发明人： Haitao Liu , Guangyu Huang , Chandra V. Mouli , Akira Goda , Deepak Chandra Pandey , Kamal M. Karda
IPC分类号： H01L29/78 , H01L29/08 , H01L29/24 , H01L29/423 , H01L29/267 , H01L27/11556 , H01L29/66 , H01L21/02 , H01L21/44 , H01L21/425 , H01L29/10 , H01L27/11582 , H01L29/786 , H01L27/1157
摘要： A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

2. 发明授权

US10608012B2 Memory devices including memory cells and related methods 有权
公开(公告)号：US10608012B2
公开(公告)日：2020-03-31
申请号：US16111357
申请日：2018-08-24
申请人： Micron Technology, Inc.
发明人： Guangyu Huang , Haitao Liu , Chandra V. Mouli , Srinivas Pulugurtha
IPC分类号： H01L27/11582 , H01L21/02 , H01L29/16 , H01L29/20 , H01L29/24 , H01L29/04 , H01L29/165 , H01L29/66 , H01L29/22 , H01L21/28
摘要： Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

3. 发明授权

US09356157B2 Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices 有权
标题翻译：包括浮栅晶体管的半导体器件和形成这种半导体器件的方法
公开(公告)号：US09356157B2
公开(公告)日：2016-05-31
申请号：US14223410
申请日：2014-03-24
申请人： Micron Technology, Inc.
发明人： Gurtej S. Sandhu , Chandra V. Mouli , Di Li
IPC分类号： H01L29/788 , H01L51/52 , H01L51/56 , H01L21/28 , H01L29/423 , H01L29/66
CPC分类号： H01L29/788 , H01L21/28273 , H01L29/42324 , H01L29/42376 , H01L29/66825 , H01L29/7883 , H01L51/5253 , H01L51/56
摘要： Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.
摘要翻译：半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。中间部分具有小于一个或两个端部的平均横截面面积。在一些实施例中，中间部分可以包括单个纳米线。在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。电子系统包括这样的半导体器件。形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

4. 发明申请

US20130252390A1 CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME 有权
标题翻译：无电容器存储器单元，器件，系统及其制造方法
公开(公告)号：US20130252390A1
公开(公告)日：2013-09-26
申请号：US13902498
申请日：2013-05-24
申请人： Micron Technology, Inc.
发明人： Fernando Gonzalez , Chandra V. Mouli
IPC分类号： H01L29/66
CPC分类号： G11C11/401 , G11C11/405 , G11C11/408 , G11C11/409 , H01L27/0705 , H01L27/108 , H01L27/10802 , H01L29/66666 , H01L29/7841
摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
摘要翻译：无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。在有源区上形成传输晶体管，用于与字线耦合。无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域有效区域，导致传输晶体管的不同可确定的阈值电压。

5. 发明授权

US11171206B2 Channel conduction in semiconductor devices 有权
公开(公告)号：US11171206B2
公开(公告)日：2021-11-09
申请号：US16509093
申请日：2019-07-11
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Haitao Liu , Si-Woo Lee , Fatma Arzum Simsek-Ege , Deepak Chandra Pandey , Chandra V. Mouli , John A. Smythe, III
IPC分类号： H01L29/06 , H01L27/108 , H01L21/762
摘要： An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

6. 发明授权

US11018255B2 Devices and systems with string drivers including high band gap material and methods of formation 有权
公开(公告)号：US11018255B2
公开(公告)日：2021-05-25
申请号：US16110217
申请日：2018-08-23
申请人： Micron Technology, Inc.
发明人： Haitao Liu , Guangyu Huang , Chandra V. Mouli , Akira Goda , Deepak Chandra Pandey , Kamal M. Karda
IPC分类号： H01L29/78 , H01L29/24 , H01L29/423 , H01L29/267 , H01L27/11556 , H01L29/66 , H01L21/02 , H01L21/44 , H01L27/11582 , H01L29/08 , H01L21/425 , H01L29/10 , H01L29/786 , H01L27/1157 , H01L29/36 , H01L29/49 , H01L29/417
摘要： A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

7. 发明授权

US09577092B2 Apparatuses having a vertical memory cell 有权
标题翻译：具有垂直存储单元的装置
公开(公告)号：US09577092B2
公开(公告)日：2017-02-21
申请号：US14517261
申请日：2014-10-17
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Rajesh N. Gupta , Srinivas Pulugurtha , Chandra V. Mouli , Wolfgang Mueller
IPC分类号： H01L29/78 , G11C11/40 , H01L27/02 , H01L27/105 , H01L29/66 , H01L27/108
CPC分类号： H01L29/7827 , G11C11/40 , H01L27/0207 , H01L27/1052 , H01L27/10855 , H01L27/10873 , H01L27/10885 , H01L27/10891 , H01L29/66666
摘要： Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.
摘要翻译：用于向垂直存取装置提供身体连接的方法，装置和系统。垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极身体区域和延伸以形成到身体区域的门的字线。一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。存储单元阵列可以包括多个垂直存取装置。

8. 发明授权

US09564576B2 Multi-bit ferroelectric memory device and methods of forming the same 有权
标题翻译：多位铁电存储器件及其形成方法
公开(公告)号：US09564576B2
公开(公告)日：2017-02-07
申请号：US14941088
申请日：2015-11-13
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , F. Daniel Gealy , D. V. Nirmal Ramaswamy , Chandra V. Mouli
IPC分类号： G11C11/22 , H01L43/02 , H01L43/12 , G11C11/56 , H01L27/115 , H01L49/02
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L28/40 , H01L43/02 , H01L43/12
摘要： Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.
摘要翻译：提供了多位铁电存储器件及其形成方法。形成多位铁电存储器件的一个示例性方法可以包括在通孔的第一侧上形成第一铁电材料，去除材料以暴露通孔的第二面，并在第二侧上形成第二铁电材料与通孔的第一侧相比具有不同的厚度。

9. 发明申请

US20160072044A1 MULTI-BIT FERROELECTRIC MEMORY DEVICE AND METHODS OF FORMING THE SAME 有权
公开(公告)号：US20160072044A1
公开(公告)日：2016-03-10
申请号：US14941088
申请日：2015-11-13
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , F. Daniel Gealy , D.V. Nirmal Ramaswamy , Chandra V. Mouli
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L28/40 , H01L43/02 , H01L43/12
摘要： Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

10. 发明申请

US20150117084A1 MULTI-BIT FERROELECTRIC MEMORY DEVICE AND METHODS OF FORMING THE SAME 有权
标题翻译：多位电磁存储器件及其形成方法
公开(公告)号：US20150117084A1
公开(公告)日：2015-04-30
申请号：US14068887
申请日：2013-10-31
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , F. Daniel Gealy , D.V. Nirmal Ramaswamy , Chandra V. Mouli
IPC分类号： H01L43/02 , H01L43/12 , H01L21/28 , G11C11/22
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L28/40 , H01L43/02 , H01L43/12
摘要： Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.
摘要翻译：提供了多位铁电存储器件及其形成方法。形成多位铁电存储器件的一个示例性方法可以包括在通孔的第一侧上形成第一铁电材料，去除材料以暴露通孔的第二面，并在第二侧上形成第二铁电材料与通孔的第一侧相比具有不同的厚度。

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