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    • 4. 发明授权
    • Cache access control system
    • 缓存访问控制系统
    • US06484242B2
    • 2002-11-19
    • US09809217
    • 2001-03-16
    • Mutsumi HosoyaMichitaka Yamamoto
    • Mutsumi HosoyaMichitaka Yamamoto
    • G06F1202
    • G06F12/0811
    • A cache access control system for dynamically conducting specification of dedicated and common regions and thereby always conducting optimum cache coherency control. In a processor, an L1 cache including an L1 data array and a directory is provided. A plurality of L2 caches are connected to each L1 cache. The L2 caches are connected to a main memory L3. An L2 cache history manager is supplied with L2 cache status information and an L2 cache access request from L2 caches. The L2 cache history manager judges an attribute (a dedicated region or a common region) of each line of L2. On the basis of the attribute, a cache coherency manager conducts coherency control of each L2 cache by using an invalidation type protocol or an update type protocol. The attribute is judged to be the common region, only in the case where a line shared by a plurality of L2 caches in the past is canceled once by the invalidation type protocol and then accessed again.
    • 高速缓存存取控制系统,用于动态地执行专用和公共区域的规范,从而始终执行最佳高速缓存一致性控制。 在处理器中,提供包括L1数据阵列和目录的L1高速缓存。 多个L2高速缓存连接到每个L1高速缓存。 L2高速缓存连接到主存储器L3。 二级缓存历史管理器提供二级高速缓存状态信息和二级高速缓存访​​问请求。 L2缓存历史管理器判断L2的每一行的属性(专用区域或公共区域)。 基于该属性,高速缓存一致性管理器通过使用无效类型协议或更新类型协议来执行每个L2高速缓存的一致性控制。 该属性被判断为公共区域,仅在过去的多个L2高速缓存共享的行被无效化协议一次取消然后再次访问的情况下。
    • 5. 发明授权
    • Dynamic logic circuit and integrated circuit device using the logic circuit
    • 动态逻辑电路和集成电路器件采用逻辑电路
    • US06278296B1
    • 2001-08-21
    • US09369199
    • 1999-08-06
    • Noboru MasudaMichitaka Yamamoto
    • Noboru MasudaMichitaka Yamamoto
    • H03K19096
    • H03K19/0963
    • In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced. Therefore, a signal delay time is reduced.
    • 在动态逻辑电路中,输入信号的从低到高跃迁与输出信号的低电平到高转换之间的信号延迟时间减小,直流电流减小,预充电所需的时间为 减少 在动态逻辑电路中,P沟道型MOS晶体管(PMOS)的源电极与高压电位Vdd侧的电源连接。 其栅电极接收时钟信号Cs。 逻辑部分包括连接在PMOS的漏电极和低电压电位Vss侧的电源之间的N沟道型MOS晶体管(NMOS)。 在与NMOS中的最接近Vss的NMOS连接的输入信号和Vss之间提供NMOS。 时钟信号Cs的反向信号与NMOS的栅电极连接。 在预充电时强制输入信号变为低电平,从而减小通电流,并减少预充电所需的时间。 因此,信号延迟时间减少。