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1. 发明授权

US5473548A Apparatus for computing power consumption of MOS transistor logic function block 失效
标题翻译：用于计算MOS晶体管逻辑功能块功耗的装置
公开(公告)号：US5473548A
公开(公告)日：1995-12-05
申请号：US100117
申请日：1993-07-30
申请人： Naoko Omori , Michio Komoda
发明人： Naoko Omori , Michio Komoda
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： Apparatus for computing power consumption in an MOS transistor logic function block include circuit information deriving unit for deriving circuit information appropriate for a logic function block of interest based on input and output varying signals to and from said logic function block, load capacitance data, and a net list, slew rate determining unit for determining an input slew rate based on information from said circuit information deriving unit, a memory section containing expressions for use in computation of power consumption caused by through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by through-current as a function of a slew rate and load capacitance, and power consumption determining unit for determining power consumption due to through-current by substituting the slew rate as determined by said slew rate determining unit and load capacitance data into the computation expression as read from said memory section.
摘要翻译：用于计算MOS晶体管逻辑功能块中的功耗的装置包括：电路信息导出单元，用于基于输入和输出与所述逻辑功能块，负载电容数据以及所述逻辑功能块的变化信号的输入和输出，导出适合于感兴趣的逻辑功能块的电路信息网络列表，转换速率确定单元，用于基于来自所述电路信息导出单元的信息确定输入转换速率;存储器部分，其包含用于计算由贯通电流引起的功耗的表达式，每个表达对应于不同的各种逻辑功能块的类型，并且表示作为转换速率和负载电容的函数的通过电流引起的功率消耗;以及功率消耗确定单元，用于通过替换由所述转换速率确定的转换速率来确定由于通过电流的功率消耗将单位和负载电容数据确定到计算表达式中从所述存储器部分读取。

2. 发明授权

US07479825B2 Clock forming method for semiconductor integrated circuit and program product for the method 有权
标题翻译：半导体集成电路的时钟形成方法和方法的程序产品
公开(公告)号：US07479825B2
公开(公告)日：2009-01-20
申请号：US11584492
申请日：2006-10-23
申请人： Michio Komoda
发明人： Michio Komoda
IPC分类号： H01L25/00
CPC分类号： G06F17/5045 , G06F2217/62
摘要： Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.
摘要翻译：每个包括预定数量的触发器（FF）的区域G1至G8被分成两组。执行这种划分，使得由边界相交的数据连接信道的数量被最小化。在两个数据连接通道（A1，A2）的交点的情况下，边界相交的数据连接通道的数量是两个，最小数量。在所有区域（G1至G4，G5至G8）分组之后，执行时钟树合成（CTS）。如果以这种方式执行时钟形成，则可以限制实际器件上的时钟偏移的增加，并且可以增加片上变化电阻。

3. 发明授权

US06552551B2 Method of producing load for delay time calculation and recording medium 失效
公开(公告)号：US06552551B2
公开(公告)日：2003-04-22
申请号：US09878352
申请日：2001-06-12
申请人： Michio Komoda , Sigeru Kuriyama
发明人： Michio Komoda , Sigeru Kuriyama
IPC分类号： G01R2726
CPC分类号： G01R31/2882 , G01R31/3191 , G01R31/31937
摘要： In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.

4. 发明授权

US06510404B1 Gate delay calculation apparatus and method thereof using parameter expressing RC model source resistance value 失效
标题翻译：门延迟计算装置及其使用表示RC模型源电阻值的参数的方法
公开(公告)号：US06510404B1
公开(公告)日：2003-01-21
申请号：US08915079
申请日：1997-08-20
申请人： Shigeru Kuriyama , Michio Komoda
发明人： Shigeru Kuriyama , Michio Komoda
IPC分类号： G06G748
CPC分类号： G06F17/5022
摘要： A gate delay calculation apparatus includes an Rs parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continuous time function, an Rs determination portion for selectively extracting the parameter prestored in the Rs parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by Rs determination portion and the output load model.
摘要翻译：门延迟计算装置包括用于预先存储用于表示RC模型的源电阻值的参数作为连续时间函数的Rs参数存储文件，Rs确定部分，用于从所述Rs参数存储文件中预先存储的参数的数量输入波形斜坡和输出负载模型;以及门延迟确定部分，用于基于由Rs确定部分提取的参数和输出负载模型表示的源电阻值来计算门延迟。

5. 发明授权

US06292043B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06292043B1
公开(公告)日：2001-09-18
申请号：US09453795
申请日：1999-12-03
申请人： Junya Shiraishi , Michio Komoda
发明人： Junya Shiraishi , Michio Komoda
IPC分类号： H03K300
CPC分类号： G06F1/10
摘要： In a semiconductor integrated circuit device, a clock buffer is arranged at the center of a chip by using a core I/O technique for arranging an input/output buffer at an arbitrary position. A clock is wired such that, with reference to a wire extending to a circuit in a chip which is farthest from the clock buffer and must be synchronously controlled. Wires extending to the other circuits are intentionally bypassed to make wires extending to all the circuits electrically equal to each other in length. Thus, a skew of a clock can be suppressed due to the isometric wiring.
摘要翻译：在半导体集成电路器件中，通过使用用于在任意位置布置输入/输出缓冲器的核心I / O技术将时钟缓冲器布置在芯片的中心。时钟被布线，使得参考延伸到与时钟缓冲器最远的芯片中的电路并且必须被同步控制的导线。延伸到其他电路的电线被有意地绕过，使得延伸到所有电路的电线在长度上彼此电相等。因此，由于等距布线可以抑制时钟的偏斜。

6. 发明授权

US07496491B2 Delay calculation method capable of calculating delay time with small margin of error 失效
标题翻译：延迟计算方法能够计算出误差小的延迟时间
公开(公告)号：US07496491B2
公开(公告)日：2009-02-24
申请号：US11174542
申请日：2005-07-06
申请人： Michio Komoda
发明人： Michio Komoda
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5031
摘要： A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during Δt1; and the one indicating that the voltage increases from V1 to E during Δt2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of Δt1, V1, and Δt2.
摘要翻译：在逻辑电路中提供延迟计算方法，其延迟计算方法能够计算误差小的延迟时间。晶体管的工作特性用固定电阻和随时间变化的电源电压表示。电源电压表示为两条直线的组合的波形：表示在固定延迟t0之前的电压在Deltat1期间增加到V1的电压; 并且在Deltat2期间电压从V1增加到E，之后保持在E的固定值。采用输入波形的形状差作为校正参数来确定Deltat1，V1和Deltat2的值。

7. 发明申请

US20070094627A1 Clock forming method for semiconductor integrated circuit and program product for the method 有权
标题翻译：半导体集成电路的时钟形成方法和方法的程序产品
公开(公告)号：US20070094627A1
公开(公告)日：2007-04-26
申请号：US11584492
申请日：2006-10-23
申请人： Michio Komoda
发明人： Michio Komoda
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62
摘要： Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.
摘要翻译：包括预定数量的触发器（FF）的区域G 1至G 8被分成两组。执行这种划分，使得由边界相交的数据连接信道的数量被最小化。在两个数据连接通道（A 1，A 2）的交点的情况下，边界相交的数据连接通道的数量是最小数量。在所有区域（G 1至G 4，G 5至G 8）分组之后，执行时钟树合成（CTS）。如果以这种方式执行时钟形成，则可以限制实际器件上的时钟偏移的增加，并且可以增加片上变化电阻。

8. 发明授权

US06546537B1 Wiring data generation method and wiring data generation apparatus allowing inconsistency between block internal line and block external lines 失效
标题翻译：接线数据生成方法和接线数据生成装置允许块内部线和块外部线之间的不一致
公开(公告)号：US06546537B1
公开(公告)日：2003-04-08
申请号：US09497172
申请日：2000-02-03
申请人： Michio Komoda
发明人： Michio Komoda
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A wiring data generation method includes the steps of generating a line in a block of a first level, carrying out layout of the block of the first level in a block of a second level higher than the first level, and generating mesh lines of the block of the second level connected to the line in the block of the first level within the block of the second level.
摘要翻译：布线数据生成方法包括以下步骤：在第一级的块中生成线，在比第一级高的第二级的块中执行第一级的块的布局，并且生成块的网格线的第二级连接到第二级的块内的第一级的块中的线。

9. 发明授权

US5729126A Master slice LSI with integrated fault detection circuitry 失效
标题翻译：具有集成故障检测电路的主分片LSI
公开(公告)号：US5729126A
公开(公告)日：1998-03-17
申请号：US757109
申请日：1996-12-02
申请人： Michio Komoda , Yoshio Inoue
发明人： Michio Komoda , Yoshio Inoue
IPC分类号： H01L21/66 , H01L21/82 , H01L27/118 , G01R31/00
CPC分类号： H01L27/118
摘要： A master slice LSI with fault detection circuitry includes a packed transistor area consisting of rows of semiconductor devices packed on a substrate. Parts of the rows are used for providing an application specific integrated circuit (ASIC). Remaining parts of the rows are used for providing fault detection circuitry for finding faulty semiconductor devices. The fault detection circuitry includes shift registers, sense amplifiers, and a decoder. The detection circuitry is provided only for those rows of semiconductor devices used for providing the intended purpose ASIC.
摘要翻译：具有故障检测电路的主分片LSI包括由衬底上的半导体器件行组成的封装晶体管区域。这些行的一部分用于提供专用集成电路（ASIC）。行的剩余部分用于提供用于找到有缺陷的半导体器件的故障检测电路。故障检测电路包括移位寄存器，读出放大器和解码器。检测电路仅用于那些用于提供预定目的ASIC的半导体器件行。

10. 发明授权

US5515291A Apparatus for calculating delay time in logic functional blocks 失效
标题翻译：用于计算逻辑功能块中的延迟时间的装置
公开(公告)号：US5515291A
公开(公告)日：1996-05-07
申请号：US929828
申请日：1992-08-14
申请人： Naoko Omori , Michio Komoda
发明人： Naoko Omori , Michio Komoda
IPC分类号： H01L21/82 , G01R31/28 , G01R31/30 , G01R31/317 , G06F15/00 , G06F15/16 , G06F17/50 , G06F19/00 , H01L21/8234 , H01L27/06 , H03K19/02
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A delay parameter calculator (13) calculates an input slew rate (tr) as a function of a layout pattern information (D12) to determine delay parameters (K) by substituting the slew rate (tr) for a delay parameter function (K(tr)). An output impedance calculator (15) calculates an impedance (RS) of an accurate output macro cell (21) as a function of a capacitance lumped constant (C) and the delay parameters (K). A delay time calculator (16) solves an equation having the output impedance (RS) as a significant parameter to correctly calculate a delay time (DT) it takes to transmit a signal from an input to an output of a logic functional block composed of MOS transistors.
摘要翻译：延迟参数计算器（13）根据布局模式信息（D12）计算输入转换速率（tr），以通过将转换速率（tr）代入延迟参数函数（K（tr））来确定延迟参数（K）））。输出阻抗计算器（15）根据电容集总常数（C）和延迟参数（K）计算精确输出宏小区（21）的阻抗（RS）。延迟时间计算器（16）解决了具有输出阻抗（RS）作为有效参数的方程，以正确地计算将信号从输入发送到由MOS组成的逻辑功能块的输出所需的延迟时间（DT）晶体管。

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