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1. 发明授权

US06593782B2 Static frequency divider with a divider ratio which can be switched over 失效
标题翻译：静态分频器，分频比可以切换
公开(公告)号：US06593782B2
公开(公告)日：2003-07-15
申请号：US09805488
申请日：2001-03-13
申请人： Michael Pierschel , Hans Gustat
发明人： Michael Pierschel , Hans Gustat
IPC分类号： H03K2100
CPC分类号： H03K23/667 , H03K3/356043
摘要： The invention is a static frequency divider with a divider ratio which can be switched over, tor use in the extremely high frequency range. In a preferred embodiment, the invention is a static frequency divider with a divider ratio which can be switched over, which includes first and second divider D- type flip-flops which each have two inputs which can be alternately activated by way of control inputs, in order to prevent the occurrence of metastable conditions. This is accomplished by connecting the successive synchronous D-type flip-flops upstream of the two divider D-type flip- flops and the control inputs of the first and second divider D-type flip-flops are connected to separate change-over switching devices.
摘要翻译：本发明是一种具有分频比的静态分频器，可以在极高频率范围内使用。在优选实施例中，本发明是具有可切换的分频比的静态分频器，其包括第一和第二分频器D-型触发器，每个具有可通过控制输入交替激活的两个输入，以防止亚稳态的发生。这通过连接两个分频器D型触发器上游的连续的同步D型触发器来实现，并且第一和第二分频器D型触发器的控制输入连接到分离的转换开关器件。

2. 发明授权

US07714420B2 Apparatus for contactlessly coupling chips 有权
标题翻译：用于非接触地耦合芯片的装置
公开(公告)号：US07714420B2
公开(公告)日：2010-05-11
申请号：US10577114
申请日：2004-10-28
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： H01L23/48 , G08C17/00 , H04B5/00
CPC分类号： H04B5/0012 , H01L23/48 , H01L25/0652 , H01L25/0655 , H01L2224/16225 , H01L2924/3011
摘要： A chip arrangement comprising a first chip having at least one first signal interface with first coupling elements arranged along a first line in a first number density and at least one second chip with at least one second signal interface with second coupling elements arranged along a second line in a second number density, where the first and second coupling elements permit contactless signal transmission between the first and second signal interfaces, where the two chips are so arranged relative to each other that coupling elements of the first and second signal interfaces can contactlessly transmit signals with each other, where the longitudinal extent of at least one of the signal interfaces along the line associated therewith is greater than the length of the overlap of the two longitudinal extents, and where one of the signal interfaces has a greater number density of coupling elements than the other.
摘要翻译：一种芯片装置，包括具有至少一个第一信号接口的第一芯片，所述第一信号接口具有沿着第一数字密度的第一线布置的第一耦合元件，以及具有至少一个第二信号接口的至少一个第二信号接口，所述第二信号接口具有沿着第二线在第二数量密度中，其中第一和第二耦合元件允许在第一和第二信号接口之间的非接触信号传输，其中两个芯片彼此相对布置，第一和第二信号接口的耦合元件可以非接触地传输信号彼此之间，其中沿着与其相关联的线的至少一个信号接口的纵向范围大于两个纵向范围的重叠的长度，并且其中一个信号接口具有较大数量的耦合元件密度比其他。

3. 发明授权

US07629841B2 Sigma-delta modulator with feedback for power amplifiers 失效
标题翻译：具有功率放大器反馈的Σ-Δ调制器
公开(公告)号：US07629841B2
公开(公告)日：2009-12-08
申请号：US11986289
申请日：2007-11-19
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： H03F3/38
CPC分类号： H03F3/217 , H03M3/368 , H03M3/458
摘要： The invention concerns an electronic circuit comprising a sigma-delta modulator and a power amplifier connected downstream thereof, wherein there is provided a feedback circuit (207) which is coupled between an output of the sigma-delta modulator and an input of the sigma-delta modulator and which includes an emulation of the signal path between the output of the sigma-delta modulator and the output of a power amplifier (107) connected downstream of said sigma-delta modulator.
摘要翻译：本发明涉及一种包括Σ-Δ调制器和连接在其下游的功率放大器的电子电路，其中提供了一个反馈电路（207），其耦合在Σ-Δ调制器的输出端和Σ-Δ调制器的输入端并且其包括在Σ-Δ调制器的输出与连接在所述Σ-Δ调制器下游的功率放大器（107）的输出之间的信号路径的仿真。

4. 发明申请

US20080180166A1 Sigma-delta modulator with feedback for power amplifiers 失效
标题翻译：具有功率放大器反馈的Σ-Δ调制器
公开(公告)号：US20080180166A1
公开(公告)日：2008-07-31
申请号：US11986289
申请日：2007-11-19
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： H03F3/38
CPC分类号： H03F3/217 , H03M3/368 , H03M3/458
摘要： The invention concerns an electronic circuit comprising a sigma-delta modulator and a power amplifier connected downstream thereof, wherein there is provided a feedback circuit (207) which is coupled between an output of the sigma-delta modulator and an input of the sigma-delta modulator and which includes an emulation of the signal path between the output of the sigma-delta modulator and the output of a power amplifier (107) connected downstream of said sigma-delta modulator.
摘要翻译：本发明涉及一种包括Σ-Δ调制器和连接在其下游的功率放大器的电子电路，其中提供了一个反馈电路（207），其耦合在Σ-Δ调制器的输出端和Σ-Δ调制器的输入端并且其包括在Σ-Δ调制器的输出与连接在所述Σ-Δ调制器下游的功率放大器（107）的输出之间的信号路径的仿真。

5. 发明申请

US20070245056A1 Processor Component 有权
标题翻译：处理器组件
公开(公告)号：US20070245056A1
公开(公告)日：2007-10-18
申请号：US10577114
申请日：2004-10-28
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： G06F13/00
CPC分类号： H04B5/0012 , H01L23/48 , H01L25/0652 , H01L25/0655 , H01L2224/16225 , H01L2924/3011
摘要： A chip arrangement comprising a first chip having at least one first signal interface with first coupling elements arranged along a first line in a first number density and at least one second chip with at least one second signal interface with second coupling elements arranged along a second line in a second number density, where the first and second coupling elements permit contactless signal transmission between the first and second signal interfaces, where the two chips are so arranged relative to each other that coupling elements of the first and second signal interfaces can contactlessly transmit signals with each other, where the longitudinal extent of at least one of the signal interfaces along the line associated therewith is greater than the length of the overlap of the two longitudinal extents, and where one of the signal interfaces has a greater number density of coupling elements than the other.
摘要翻译：一种芯片装置，包括具有至少一个第一信号接口的第一芯片，所述第一信号接口具有沿着第一数字密度的第一线布置的第一耦合元件，以及具有至少一个第二信号接口的至少一个第二信号接口，所述第二信号接口具有沿着第二线在第二数量密度中，其中第一和第二耦合元件允许在第一和第二信号接口之间的非接触信号传输，其中两个芯片彼此相对布置，第一和第二信号接口的耦合元件可以非接触地传输信号彼此之间，其中沿着与其相关联的线的至少一个信号接口的纵向范围大于两个纵向范围的重叠的长度，并且其中一个信号接口具有较大数量的耦合元件密度比其他。

6. 发明申请

US20100141495A1 Digital-Analog Converter 有权
标题翻译：数模转换器
公开(公告)号：US20100141495A1
公开(公告)日：2010-06-10
申请号：US12587105
申请日：2009-09-30
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： H03M1/66
CPC分类号： H03M1/0682 , H03K19/0136 , H03K19/01806 , H03M1/1004 , H03M1/1009 , H03M1/745
摘要： A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.1) of a second transistor (210), the respective first signal terminals of the first and second transistors are additionally connected by way of a constant current source (212 and 214) to a ground terminal (216), and wherein a respective time-constant bias voltage is applied at a respective control terminal (208.2 and 210.2) of the first and second transistors.
摘要翻译：一种用于将多个差分数字输入信号转换为差分模拟输出信号的并行数模转换器，包括一组1位数模转换器（200），它们分别包括中间存储单元（202）和当前单元（201），其适于根据中间存储单元的逻辑状态将相应的输出电流馈送到第一（204）或第二输出触点（206），其中中间存储单元的两个输出中的第一个输出存储单元（202）通过输入电阻器（220）连接到第一晶体管（208）的第一信号端子（208.1），并且中间存储单元（202）的两个输出端中的第二个输出端连接的输入电阻器（218）连接到第二晶体管（210）的第一信号端子（210.1），第一和第二晶体管的各个第一信号端子通过恒定电流源（212和214）附加地连接到一个地面终端（216），并且其中在第一和第二晶体管的相应控制端（208.2和210.2）处施加相应的时间常数偏置电压。

7. 发明申请

US20080129565A1 Apparatus for and method of sigma-delta modulation 审中-公开
标题翻译： Σ-Δ调制装置和方法
公开(公告)号：US20080129565A1
公开(公告)日：2008-06-05
申请号：US11985334
申请日：2007-11-14
申请人： Hans Gustat , Pylyp Ostrovskyy
发明人： Hans Gustat , Pylyp Ostrovskyy
IPC分类号： H03M3/00
CPC分类号： H03M3/498
摘要： The invention concerns an electronic circuit comprising a sigma-delta modulator (200) and a clock generator (210) which outputs a clock signal (clk(t)) which is suitable for clock control of the sigma-delta modulator (200), wherein the clock generator is adapted to set the clock rate of the clock signal (clk(t)) variably in dependence on an instantaneous frequency of the input signal (x(t)).
摘要翻译：本发明涉及一种包括Σ-Δ调制器（200）和时钟发生器（210）的电子电路，其输出适合于Σ-Δ调制器（200）的时钟控制的时钟信号（clk（t）），其中时钟发生器适于根据输入信号的瞬时频率（x（t））可变地设置时钟信号的时钟速率（clk（t））。

8. 发明授权

US07924196B2 Digital-analog converter 有权
标题翻译：数模转换器
公开(公告)号：US07924196B2
公开(公告)日：2011-04-12
申请号：US12587105
申请日：2009-09-30
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： H03M1/66
CPC分类号： H03M1/0682 , H03K19/0136 , H03K19/01806 , H03M1/1004 , H03M1/1009 , H03M1/745
摘要： A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.1) of a second transistor (210), the respective first signal terminals of the first and second transistors are additionally connected by way of a constant current source (212 and 214) to a ground terminal (216), and wherein a respective time-constant bias voltage is applied at a respective control terminal (208.2 and 210.2) of the first and second transistors.
摘要翻译：一种用于将多个差分数字输入信号转换为差分模拟输出信号的并行数模转换器，包括一组1位数模转换器（200），它们分别包括中间存储单元（202）和当前单元（201），其适于根据中间存储单元的逻辑状态将相应的输出电流馈送到第一（204）或第二输出触点（206），其中中间存储单元的两个输出中的第一个输出存储单元（202）通过输入电阻器（220）连接到第一晶体管（208）的第一信号端子（208.1），并且中间存储单元（202）的两个输出端中的第二个输出端连接的输入电阻器（218）连接到第二晶体管（210）的第一信号端子（210.1），第一和第二晶体管的各个第一信号端子通过恒定电流源（212和214）附加地连接到一个地面终端（216），并且其中在第一和第二晶体管的相应控制端（208.2和210.2）处施加相应的时间常数偏置电压。

9. 发明授权

US06369611B1 Sequential circuit for high frequency clocking 失效
标题翻译：高频时钟顺序电路
公开(公告)号：US06369611B1
公开(公告)日：2002-04-09
申请号：US09443917
申请日：1999-11-19
申请人： Hans Gustat
发明人： Hans Gustat
IPC分类号： G06F738
CPC分类号： H03K19/01742
摘要： Circuit arrangement, and a method of its operation, for substantially reducing the running times in clocked logic circuits by eliminating conventional storage registers and by controlling the signal flow by parallel connection to the output of a gate or other signal transmitting circuit component of an additional current source which may be changed by the clock pulse.
摘要翻译：电路布置及其操作方法，通过消除常规存储寄存器并且通过并联连接到门或其它信号发送电路组件的附加电流的输出来大大减少时钟逻辑电路中的运行时间源可以被时钟脉冲改变。

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