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1. 发明授权

US06579759B1 Formation of self-aligned buried strap connector 失效
标题翻译：自对准埋地连接器的形成
公开(公告)号：US06579759B1
公开(公告)日：2003-06-17
申请号：US10227396
申请日：2002-08-23
申请人： Michael Patrick Chudzik , Jochen Beintner , Ramachandra Divakaruni , Rajarao Jammy
发明人： Michael Patrick Chudzik , Jochen Beintner , Ramachandra Divakaruni , Rajarao Jammy
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10841 , H01L29/66181
摘要： In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.
摘要翻译：在垂直晶体管DRAM单元中，通过以下方式解决了深沟槽电容器的节点与垂直晶体管的下电极之间可靠的电连接的问题; 沉积临时绝缘体层，在临时绝缘体上方的沟槽壁上形成垂直间隔物，然后剥离绝缘体以露出衬底壁; 将掺杂剂扩散到衬底壁中以形成埋入带的自对准延伸部; 沉积最后的栅极绝缘体; 然后形成DRAM单元的上部。

2. 发明授权

US06998666B2 Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
标题翻译：氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响
公开(公告)号：US06998666B2
公开(公告)日：2006-02-14
申请号：US10707754
申请日：2004-01-09
申请人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
发明人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10894
摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.
摘要翻译：一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极导体和掺硼通道。该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。然后在DRAM单元的两侧的沟槽中形成隔离区。此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

3. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

4. 发明申请

US20050151181A1 NITRIDED STI LINER OXIDE FOR REDUCED CORNER DEVICE IMPACT ON VERTICAL DEVICE PERFORMANCE 有权
标题翻译：用于减少角膜器件的氮化硅氧化物对垂直器件性能的影响
公开(公告)号：US20050151181A1
公开(公告)日：2005-07-14
申请号：US10707754
申请日：2004-01-09
申请人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
发明人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
IPC分类号： H01L21/8242 , H01L21/762 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10894
摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.
摘要翻译：一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极导体和掺硼通道。该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。然后在DRAM单元的两侧的沟槽中形成隔离区。此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

5. 发明授权

US06746933B1 Pitcher-shaped active area for field effect transistor and method of forming same 失效
公开(公告)号：US06746933B1
公开(公告)日：2004-06-08
申请号：US09999803
申请日：2001-10-26
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

6. 发明授权

US07737502B2 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain 有权
标题翻译：用于提高源/漏极的应变Si / SGOI结构上的多栅极氧化和侧壁保护的提高的STI工艺
公开(公告)号：US07737502B2
公开(公告)日：2010-06-15
申请号：US11351801
申请日：2006-02-10
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Byeong Y. Kim
IPC分类号： H01L27/088
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

7. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

8. 发明申请

US20080111184A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20080111184A1
公开(公告)日：2008-05-15
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

9. 发明申请

US20090101995A1 PROCESS FOR FABRICATION OF FINFETs 有权
标题翻译： FINFET制造工艺
公开(公告)号：US20090101995A1
公开(公告)日：2009-04-23
申请号：US12342655
申请日：2008-12-23
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

10. 发明申请

US20050277271A1 RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED Si/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN 失效
标题翻译：用于高压源/排水的应变Si / SGOI结构的多栅极氧化物和栅极保护的提高过程
公开(公告)号：US20050277271A1
公开(公告)日：2005-12-15
申请号：US10709963
申请日：2004-06-09
申请人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
发明人： Jochen Beintner , Gary Bronner , Ramachandra Divakaruni , Byeong Kim
IPC分类号： C30B1/00 , H01L21/20 , H01L21/336 , H01L21/36 , H01L21/762 , H01L29/10 , H01L29/51 , H01L29/786
CPC分类号： H01L29/66628 , H01L21/76243 , H01L21/76251 , H01L29/1054 , H01L29/41783 , H01L29/516 , H01L29/517 , H01L29/6653 , H01L29/66742 , H01L29/7842 , H01L29/78687 , Y10S438/938
摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.
摘要翻译：本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。本发明还提供了一种形成这种结构的方法。在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

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