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1. 发明授权

US09099461B2 Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure 有权
标题翻译：在半导体器件中制造尺寸等效的氧化物厚度栅极叠层的方法及相关设计结构
公开(公告)号：US09099461B2
公开(公告)日：2015-08-04
申请号：US13490740
申请日：2012-06-07
申请人： Michael P. Chudzik , Min Dai , Jinping Liu , Paul A. Ronsheim , Joseph F. Shepard, Jr. , Shahab Siddiqui
发明人： Michael P. Chudzik , Min Dai , Jinping Liu , Paul A. Ronsheim , Joseph F. Shepard, Jr. , Shahab Siddiqui
IPC分类号： H01L21/66 , H01L29/51 , H01L21/28
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28202 , H01L22/12 , H01L22/26 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
摘要翻译：公开了一种形成半导体器件的方法。该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。

2. 发明授权

US08492290B2 Fabrication of silicon oxide and oxynitride having sub-nanometer thickness 有权
标题翻译：具有亚纳米厚度的氧化硅和氮氧化物的制造
公开(公告)号：US08492290B2
公开(公告)日：2013-07-23
申请号：US13164891
申请日：2011-06-21
申请人： Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Jinping Liu
发明人： Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Jinping Liu
IPC分类号： H01L21/31
CPC分类号： H01L21/02052 , H01L21/0214 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/02301 , H01L21/02332 , H01L21/0234 , H01L21/28211 , H01L21/28238
摘要： A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å.
摘要翻译：一种制造含硅氧化物层的方法，包括在半导体衬底的表面上提供化学氧化物层，在1000℃或更高的温度下在无氧环境中除去化学氧化物层，以提供裸露在半导体衬底的表面上，以1000℃的温度将半导体衬底的裸露表面的含氧气体首次引入半导体衬底的裸露表面。然后在第二时间内将温度降至室温同时保持含氧气体的流速，从而提供厚度范围从0.5到10的含硅氧化物层。

3. 发明授权

US09029959B2 Composite high-k gate dielectric stack for reducing gate leakage 有权
标题翻译：用于减少栅极泄漏的复合高k栅极电介质堆叠
公开(公告)号：US09029959B2
公开(公告)日：2015-05-12
申请号：US13537101
申请日：2012-06-29
申请人： MaryJane Brodsky , Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Yanfeng Wang , Jinping Liu
发明人： MaryJane Brodsky , Michael P. Chudzik , Min Dai , Joseph F. Shepard, Jr. , Shahab Siddiqui , Yanfeng Wang , Jinping Liu
IPC分类号： H01L29/49 , H01L21/02 , H01L21/28 , H01L21/3115 , H01L21/8234 , H01L29/51
CPC分类号： H01L21/02321 , H01L21/28194 , H01L21/3115 , H01L21/823462 , H01L29/513 , H01L29/517
摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.
摘要翻译：复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

4. 发明授权

US06770526B2 Silicon nitride island formation for increased capacitance 有权
公开(公告)号：US06770526B2
公开(公告)日：2004-08-03
申请号：US10294100
申请日：2002-11-14
申请人： Michael P. Chudzik , Jochen Beintner , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Jochen Beintner , Joseph F. Shepard, Jr.
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L27/10817 , H01L29/66181 , H01L29/945
摘要： A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

5. 发明授权

US06653246B2 High dielectric constant materials 失效
标题翻译：高介电常数材料
公开(公告)号：US06653246B2
公开(公告)日：2003-11-25
申请号：US10338481
申请日：2003-01-08
申请人： Michael P. Chudzik , Lawrence Clevenger , Louis L. Hsu , Deborah A. Neumayer , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Lawrence Clevenger , Louis L. Hsu , Deborah A. Neumayer , Joseph F. Shepard, Jr.
IPC分类号： H01L2131
CPC分类号： C23C16/45525 , C23C16/40 , C23C16/56 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/3162
摘要： A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80%
摘要翻译：一种用于集成电路结构的方法和结构，其包括在衬底上引入前体，氧化前体并加热前体。前体的引入和氧化以使得在衬底上形成无定形玻璃电介质的方式进行。在将前体引入基片之前，该方法优选地包括清洁基底。前体的引入以与玻璃膜的形成一致的摩尔比进行，并且可以包括使用20％-50％La 2 O 3和50％-80％之间的比率的La 2 O 3和Al 2 O 3的原子级化学气相沉积

6. 发明授权

US08241981B1 Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor 失效
标题翻译：制造深沟槽（DT）金属 - 绝缘体 - 金属（MIM）电容器的方法
公开(公告)号：US08241981B1
公开(公告)日：2012-08-14
申请号：US13017108
申请日：2011-01-31
申请人： Rishikesh Krishnan , Joseph F. Shepard, Jr. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
发明人： Rishikesh Krishnan , Joseph F. Shepard, Jr. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/1087 , H01L28/40 , H01L29/66181
摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.
摘要翻译：一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

7. 发明授权

US07871933B2 Combined stepper and deposition tool 有权
标题翻译：组合步进和沉积工具
公开(公告)号：US07871933B2
公开(公告)日：2011-01-18
申请号：US11164684
申请日：2005-12-01
申请人： Michael P. Chudzik , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Joseph F. Shepard, Jr.
IPC分类号： H01L21/311
CPC分类号： G03F7/168 , G03F7/0035
摘要： A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material is removed by the application of UV light through the mask of the stepper, thereby eliminating the bake and development steps of the prior art method. Similarly, a flood exposure of UV eliminates the cleaning steps of the prior art method.
摘要翻译：步进机与在形成集成电路的过程中沉积材料层的硬件结合在一起，从而执行沉积，图案化和清洁，而不会将晶片暴露于工具之间的转移并结合复合工具中的三种工具的功能。通过施加UV光通过步进器的掩模去除图案限定材料，从而消除现有技术方法的烘烤和显影步骤。类似地，UV的泛滥暴露消除了现有技术方法的清洁步骤。

8. 发明授权

US07459913B2 Methods for the determination of film continuity and growth modes in thin dielectric films 失效
标题翻译：薄介电膜中膜连续性和生长模式的测定方法
公开(公告)号：US07459913B2
公开(公告)日：2008-12-02
申请号：US10710947
申请日：2004-08-13
申请人： Michael P. Chudzik , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Joseph F. Shepard, Jr.
IPC分类号： G01N27/60 , G01R31/26 , G01R27/08
CPC分类号： H01L21/02263 , C23C16/45525 , C23C16/52 , H01L21/0228 , H01L21/314
摘要： A method for determining film continuity and growth modes in thin dielectric films includes: depositing a material on the substrate using a first value of a growth metric; depositing an amount of charge on a surface of the material; repetitively measuring a surface voltage of the material until an onset of tunneling to provide a Vtunnel (or Etunnel) value; repeating the above steps for different values of the growth metric; and comparing the Vtunnel (or Etunnel) values for different values of the growth metric to provide a measure of the continuity of the material on the substrate. The growth modes of the material can be determined by comparing the first derivative of the Vtunnel or Etunnel per growth metric curve versus the growth metric, and examining the linearity of the results of the comparison. The growth metric parameters may include thickness, time, precursor cycles, or temperature.
摘要翻译：用于确定薄介电膜中的膜连续性和生长模式的方法包括：使用生长度量的第一值将材料沉积在衬底上; 在所述材料的表面上沉积一定量的电荷; 重复地测量材料的表面电压，直到隧道开始，以提供Vtunnel（或Etunnel）值; 对生长度量的不同值重复上述步骤; 以及比较生长度量值的不同值的Vtunnel（或Etunnel）值，以提供衬底上材料的连续性的量度。材料的生长模式可以通过比较Vtunnel或Etunnel的每个生长度量曲线的一阶导数与生长指标，并检查比较结果的线性来确定。生长度量参数可以包括厚度，时间，前体循环或温度。

9. 发明授权

US07186625B2 High density MIMCAP with a unit repeatable structure 失效
标题翻译：具有单位可重复结构的高密度MIMCAP
公开(公告)号：US07186625B2
公开(公告)日：2007-03-06
申请号：US10709768
申请日：2004-05-27
申请人： Michael P. Chudzik , Louis L. Hsu , Joseph F. Shepard, Jr. , William R. Tonti
发明人： Michael P. Chudzik , Louis L. Hsu , Joseph F. Shepard, Jr. , William R. Tonti
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure, apparatus and method for utilizing vertically interdigitated electrodes serves to increase the capacitor area surface while maintaining a minimal horizontal foot print. Since capacitance is proportional to the surface area the structure enables continual use of current dielectric materials such as Si3N4 at current thicknesses. In a second embodiment of the interdigitated MIMCAP structure the electrodes are formed in a spiral fashion which serves to increase the physical strength of the MIMCAP. Also included is a spiral shaped capacitor electrode which lends itself to modular design by offering a wide range of discrete capacitive values easily specified by the circuit designer.
摘要翻译：用于利用垂直交错电极的结构，装置和方法用于增加电容器面积，同时保持最小的水平脚印。由于电容与表面积成比例，因此该结构能够连续使用当前厚度的当前介电材料，例如Si 3 N 4。在叉指MIMCAP结构的第二实施例中，电极以螺旋方式形成，其用于增加MIMCAP的物理强度。还包括螺旋形电容器电极，其通过提供电路设计者容易指定的宽范围的离散电容值来适应模块化设计。

10. 发明授权

US06541331B2 Method of manufacturing high dielectric constant material 失效
标题翻译：制造高介电常数材料的方法
公开(公告)号：US06541331B2
公开(公告)日：2003-04-01
申请号：US09924548
申请日：2001-08-09
申请人： Michael P. Chudzik , Lawrence Clevenger , Louis L. Hsu , Deborah A. Neumayer , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Lawrence Clevenger , Louis L. Hsu , Deborah A. Neumayer , Joseph F. Shepard, Jr.
IPC分类号： H01L218242
CPC分类号： C23C16/45525 , C23C16/40 , C23C16/56 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/3162
摘要： A process of forming a high-k dielectric in an integrated circuit structure is disclosed. The process cleans a substrate to remove residual organic materials and strip native oxide from the surface of the substrate. Next, the process introduces precursors on the substrate in molar ratios consistent with formation of dielectric glass films. Following that, the process oxidizes the precursors, heats the precursors, and cools the precursors at a rate that avoids crystallization of the precursors.
摘要翻译：公开了一种在集成电路结构中形成高k电介质的工艺。该方法清洗基材以除去残余的有机材料并从基材的表面剥离天然氧化物。接下来，该方法以与电介质玻璃膜的形成一致的摩尔比在基材上引入前体。之后，该方法氧化前体，加热前体，并以避免前体结晶的速率冷却前体。

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