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    • 3. 发明授权
    • System and method for pendant bus for serially chaining multiple portable pendant peripherals
    • 用于串联多个便携式吊坠外围设备的吊坠母线的系统和方法
    • US07386638B2
    • 2008-06-10
    • US11186273
    • 2005-07-21
    • David William VothMichael P. Calligaro
    • David William VothMichael P. Calligaro
    • G06F13/00G06F3/00G06F13/42
    • H04L12/407H04L12/40H04L69/22
    • A communications system is arranged for serially chaining multiple portable pendant peripherals to a portable host device. The system enables multiple low power input/output peripherals to communicate over a bi-directional data line with a portable host device such as a PDA or cellular phone. Fixed-length data packets are employed in a store-and-forward approach between the host device and the pendant peripherals. An upstream pendant system component controls a unidirectional clock signal that regulates data transfers to or from the host device and a downstream pendant peripheral. A device identification field associated with the data packet is incremented or decremented as the data packet is forwarded along the pendant bus chain until it reaches its destination.
    • 通信系统被安排用于将多个便携式吊坠周边设备串连到便携式主机设备。 该系统使得多个低功率输入/输出外围设备能够通过双向数据线与诸如PDA或蜂窝电话的便携式主机设备进行通信。 在主机设备和垂饰外设之间的存储转发方法中采用固定长度的数据包。 上游侧挂系统组件控制单向时钟信号,其调节到主机设备和下游侧设备的数据传输。 与数据分组相关联的设备识别字段随着数据分组沿着垂悬总线链转发直到到达其目的地而递增或递减。
    • 5. 发明授权
    • System and method for initializing a memory device from block oriented NAND flash
    • 从面向块的NAND闪存初始化存储器件的系统和方法
    • US07340566B2
    • 2008-03-04
    • US10611129
    • 2003-06-30
    • David William VothAvi R. Geiger
    • David William VothAvi R. Geiger
    • G06F12/00
    • G11C7/20
    • Described is a system and method for initializing other memory from block oriented NAND flash by central processing units (CPUs) designed for non-NAND flash. The system employs a sequential loader that avoids the use of branches, loops, and the like, to enable a portion of the sequential loader to be sequentially fetched and executed by the CPU. The fetched and executed portion of the sequential loader is configured to copy additional instructions from NAND flash into random-access memory, such that the CPU may be fully booted from the sequential loader by executing code that has been copied into the random-access memory.
    • 描述了一种通过为非NAND闪存设计的中央处理单元(CPU)从面向块的NAND闪存初始化其他存储器的系统和方法。 系统采用顺序加载器,避免使用分支,循环等,以使得顺序加载器的一部分能够由CPU顺序地获取和执行。 顺序加载器的获取和执行部分被配置为将来自NAND闪存的附加指令复制到随机存取存储器中,使得CPU可以通过执行已被复制到随机存取存储器中的代码从顺序加载器完全引导。