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1. 发明授权

US06977194B2 Structure and method to improve channel mobility by gate electrode stress modification 有权
标题翻译：通过栅电极应力改变来提高沟道迁移率的结构和方法
公开(公告)号：US06977194B2
公开(公告)日：2005-12-20
申请号：US10695752
申请日：2003-10-30
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

2. 发明授权

US07750410B2 Structure and method to improve channel mobility by gate electrode stress modification 失效
标题翻译：通过栅电极应力改变来提高沟道迁移率的结构和方法
公开(公告)号：US07750410B2
公开(公告)日：2010-07-06
申请号：US11175223
申请日：2005-07-07
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L29/72
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2 ，NiSi或PdSi）。在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

3. 发明授权

US07262087B2 Dual stressed SOI substrates 有权
公开(公告)号：US07262087B2
公开(公告)日：2007-08-28
申请号：US10905062
申请日：2004-12-14
申请人： Dureseti Chidambarrao , Bruce B. Doris , Oleg Gluschenkov , Omer H. Dokumaci , Huilong Zhu
发明人： Dureseti Chidambarrao , Bruce B. Doris , Oleg Gluschenkov , Omer H. Dokumaci , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

4. 发明授权

US07312134B2 Dual stressed SOI substrates 有权
标题翻译：双重应力SOI衬底
公开(公告)号：US07312134B2
公开(公告)日：2007-12-25
申请号：US11741441
申请日：2007-04-27
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Huilong Zhu
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

5. 发明授权

US07488658B2 Stressed semiconductor device structures having granular semiconductor material 有权
标题翻译：具有粒状半导体材料的强调半导体器件结构
公开(公告)号：US07488658B2
公开(公告)日：2009-02-10
申请号：US11531372
申请日：2006-09-13
申请人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

6. 发明申请

US20080064172A1 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 有权
标题翻译：具有颗粒半导体材料的应力半导体器件结构
公开(公告)号：US20080064172A1
公开(公告)日：2008-03-13
申请号：US11531372
申请日：2006-09-13
申请人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B. Doris , Michael P. Belyansky , Diane C. Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

7. 发明授权

US07122849B2 Stressed semiconductor device structures having granular semiconductor material 失效
公开(公告)号：US07122849B2
公开(公告)日：2006-10-17
申请号：US10707018
申请日：2003-11-14
申请人： Bruce B Doris , Michael P Belyansky , Diane C Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce B Doris , Michael P Belyansky , Diane C Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

8. 发明授权

US07732288B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07732288B2
公开(公告)日：2010-06-08
申请号：US12367764
申请日：2009-02-09
申请人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/0843 , H01L21/26506 , H01L21/26586 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
摘要翻译：一种半导体结构的制造方法。新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。提供半导体层上的半导体层和栅极堆叠。半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。去除第一和第二半导体区域。除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。

9. 发明申请

US20090142894A1 METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20090142894A1
公开(公告)日：2009-06-04
申请号：US12367764
申请日：2009-02-09
申请人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
发明人： Huilong Zhu , Lawrence A. Clevenger , Omer H. Dokumaci , Oleg Gluschenkov , Kaushik A. Kumar , Carl J. Radens , Dureseti Chidambarrao
IPC分类号： H01L21/336
CPC分类号： H01L29/0843 , H01L21/26506 , H01L21/26586 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.
摘要翻译：一种半导体结构的制造方法。新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。提供半导体层上的半导体层和栅极堆叠。半导体层包括（i）栅极叠层正下方的沟道区，以及（ii）基本上不被栅极叠层覆盖的第一和第二半导体区，并且其中沟道区设置在第一和第二半导体区之间。去除第一和第二半导体区域。除去去除的第一和第二半导体区域正下方的区域，以便分别形成第一和第二源极/漏极区域，使得第一和第二源极/漏极区域的顶表面在通道区域的顶表面之下。

10. 发明授权

US06873010B2 High performance logic and high density embedded dram with borderless contact and antispacer 失效
标题翻译：高性能逻辑和高密度嵌入式电脑，无边界接触和对抗
公开(公告)号：US06873010B2
公开(公告)日：2005-03-29
申请号：US10682430
申请日：2003-10-10
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allen Mandelman
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Bruce Bennett Doris , Oleg Gluschenkov , Rajarao Jammy , Jack Allen Mandelman
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10891 , H01L27/10894
摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
摘要翻译：集成电路包括具有由最小光刻特征分隔的阵列晶体管和由扩散阻挡层封装的非硅化金属位线的存储单元，而高性能逻辑晶体管可以形成在同一芯片上而不损害包括有效通道在内的性能， /漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离在逻辑晶体管中。

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