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1. 发明授权

US07754594B1 Method for tuning the threshold voltage of a metal gate and high-k device 失效
标题翻译：调整金属栅极和高k器件阈值电压的方法
公开(公告)号：US07754594B1
公开(公告)日：2010-07-13
申请号：US12359434
申请日：2009-01-26
申请人： Michael P Chudzik , Michael A Gribelyuk , Rashmi Jha , Renee T Mo , Naim Moumen , Keith Kwong Hon Wong
发明人： Michael P Chudzik , Michael A Gribelyuk , Rashmi Jha , Renee T Mo , Naim Moumen , Keith Kwong Hon Wong
IPC分类号： H01L21/3205
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966
摘要： A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.
摘要翻译：金属栅极和高k电介质器件包括衬底，衬底顶部的界面层，界面层顶部的高k电介质层，高k电介质层顶部的金属膜，帽层在金属膜的顶部上，金属栅极层位于盖层的顶部。调整金属膜的厚度和盖层的厚度，使得帽层材料的靶浓度存在于金属膜和高k电介质层的界面处。

2. 发明申请

US20090294920A1 METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF 有权
标题翻译：使用光电隔离膜形成双高金属栅的方法及其结构
公开(公告)号：US20090294920A1
公开(公告)日：2009-12-03
申请号：US12132146
申请日：2008-06-03
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L23/58 , H01L21/311
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

3. 发明授权

US07915115B2 Method for forming dual high-k metal gate using photoresist mask and structures thereof 有权
标题翻译：使用光致抗蚀剂掩模及其结构形成双高k金属栅的方法
公开(公告)号：US07915115B2
公开(公告)日：2011-03-29
申请号：US12132146
申请日：2008-06-03
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L29/72
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

4. 发明授权

US08120144B2 Method for forming dual high-K metal gate using photoresist mask and structures thereof 失效
标题翻译：使用光致抗蚀剂掩模及其结构形成双高K金属栅的方法
公开(公告)号：US08120144B2
公开(公告)日：2012-02-21
申请号：US13018888
申请日：2011-02-01
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L29/72
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

5. 发明申请

US20110121436A1 METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF 失效
标题翻译：使用光电隔离膜形成双高金属栅的方法及其结构
公开(公告)号：US20110121436A1
公开(公告)日：2011-05-26
申请号：US13018888
申请日：2011-02-01
申请人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
发明人： Michael P. Chudzik , Rashmi Jha , Naim Moumen , Keith Kwong Hon Wong , Ying H. Tsang
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L21/31133 , H01L21/31127 , H01L21/31138
摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.
摘要翻译：公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

6. 发明申请

US20090308636A1 IN-SITU SILICON CAP FOR METAL GATE ELECTRODE 失效
标题翻译：用于金属门电极的现场硅封头
公开(公告)号：US20090308636A1
公开(公告)日：2009-12-17
申请号：US12137745
申请日：2008-06-12
申请人： Michael P Chudzik , Troy Graves-Abe , Rashmi Jha , Renee T. Mo , Keith Kwong Hon Wong
发明人： Michael P Chudzik , Troy Graves-Abe , Rashmi Jha , Renee T. Mo , Keith Kwong Hon Wong
IPC分类号： H01L21/28 , H01B5/14
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/324 , H01L29/517
摘要： Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.
摘要翻译：公开了通过沉积原位硅（Si）帽来改善金属栅极器件的性能的结构和方法。将包括基板和电介质层的晶片通过脱气加热，然后冷却至约室温。然后沉积金属层，然后在其上沉积原位Si盖。在加热，冷却和金属沉积过程中，Si盖被沉积成没有真空断裂，即在相同的主框架或相同的室中。因此，在随后的处理期间可用于层间氧化物再生长的氧气量以及金属栅极中捕获的氧量减少。

7. 发明授权

US08138041B2 In-situ silicon cap for metal gate electrode 失效
标题翻译：用于金属栅极的原位硅帽
公开(公告)号：US08138041B2
公开(公告)日：2012-03-20
申请号：US12137745
申请日：2008-06-12
申请人： Michael P. Chudzik , Troy Graves-Abe , Rashmi Jha , Renee T. Mo , Keith Kwong Hon Wong
发明人： Michael P. Chudzik , Troy Graves-Abe , Rashmi Jha , Renee T. Mo , Keith Kwong Hon Wong
IPC分类号： H01L21/203
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/324 , H01L29/517
摘要： Structure and method of improving the performance of metal gate devices by depositing an in-situ silicon (Si) cap are disclosed. A wafer including a substrate and a dielectric layer is heated through a degas process, and then cooled to approximately room temperature. A metal layer is then deposited, and then an in-situ Si cap is deposited thereon. The Si cap is deposited without vacuum break, i.e., in the same mainframe or in the same chamber, as the heating, cooling and metal deposition processes. As such, the amount of oxygen available for interlayer oxide regrowth during subsequent processing is reduced as well as the amount oxygen trapped in the metal gate.
摘要翻译：公开了通过沉积原位硅（Si）帽来改善金属栅极器件的性能的结构和方法。将包括基板和电介质层的晶片通过脱气加热，然后冷却至约室温。然后沉积金属层，然后在其上沉积原位Si盖。在加热，冷却和金属沉积过程中，Si盖被沉积成没有真空断裂，即在相同的主框架或相同的室中。因此，在随后的处理期间可用于层间氧化物再生长的氧气量以及金属栅极中捕获的氧量减少。

8. 发明申请

US20090152651A1 GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER 审中-公开
标题翻译：具有氧气捕获层的门盖结构
公开(公告)号：US20090152651A1
公开(公告)日：2009-06-18
申请号：US11958595
申请日：2007-12-18
申请人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517
摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.
摘要翻译：晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。栅极堆叠形成在沟道区域上方的衬底上。该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。最后，多晶硅帽与第二金属氮化物层接触（在）上。

9. 发明申请

US20100244206A1 METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS 审中-公开
标题翻译：用于高K金属栅极晶体管的阈值电压控制和驱动电流改进的方法和结构
公开(公告)号：US20100244206A1
公开(公告)日：2010-09-30
申请号：US12414794
申请日：2009-03-31
申请人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L23/00 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
摘要翻译：形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

10. 发明申请

US20100187610A1 SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE 有权
标题翻译：具有双金属门的半导体器件及其制造方法
公开(公告)号：US20100187610A1
公开(公告)日：2010-07-29
申请号：US12359520
申请日：2009-01-26
申请人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
发明人： Unoh Kwon , Siddarth A. Krishnan , Takashi Ando , Michael P. Chudzik , Martin M. Frank , William K. Henson , Rashmi Jha , Yue Liang , Vijay Narayanan , Ravikumar Ramachandran , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/517
摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.
摘要翻译：半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且第三金属层，第三金属层设置在第二中间层上。或者，省略第一金属层。制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

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