专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6108756A Semaphore enhancement to allow bank selection of a shared resource memory device 失效
标题翻译：信号量增强，允许银行选择共享资源存储设备
公开(公告)号：US6108756A
公开(公告)日：2000-08-22
申请号：US785662
申请日：1997-01-17
申请人： Michael Miller , John Mick , Jeff Smith , Mark Baumann
发明人： Michael Miller , John Mick , Jeff Smith , Mark Baumann
IPC分类号： G06F9/46 , G06F12/02
CPC分类号： G06F9/52
摘要： A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
摘要翻译：具有用于与左（205）和右（206）电子设备进行通信的左（203）和右（204）端口的存储设备（201）包括存储体（401-0差分401-7），信号量逻辑（302），以及端口耦合电路（403,404,405-0，差异405-7,406-0，差异406-7,407-0，差异407-7）。信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号（313,314），并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口银行存取授权信号。存储设备中还包括邮箱寄存器（2500-0L DIFFERENCE 2500-3L，2500-0R差分2500-3R），中断产生电路（2514-0L差分2514-3L，2514-0R差分2514-3R，2900 ，3000,307,308）以及中断状态和原因寄存器（3101L差分3102L，3101R差分3102R，3301L差分3302L，3301R差分3302R）。左右电子设备使用邮箱寄存器相互发送消息，无需等待。中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备，并且当消息已被写入其中一个邮箱寄存器时。中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息，哪些邮箱寄存器包含用于它们的消息。

2. 发明授权

US06212607B1 Multi-ported memory architecture using single-ported RAM 失效
标题翻译：使用单端口RAM的多端口存储器架构
公开(公告)号：US06212607B1
公开(公告)日：2001-04-03
申请号：US08783923
申请日：1997-01-17
申请人： Michael Miller , John Mick , Jeff Smith , Mark Baumann , Chris Schott
发明人： Michael Miller , John Mick , Jeff Smith , Mark Baumann , Chris Schott
IPC分类号： G06F1200
CPC分类号： G11C7/1075 , G11C2207/104
摘要： A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0˜401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0˜405-7, 406-0˜406-7, 407-0˜407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L˜2500-3L, 2500-0R˜2500-3R), interrupt generating circuitry (2514-0L˜2514-3L, 2514-0R˜2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L˜3102L, 3101R˜3102R, 3301L˜3302L, 3301R˜3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
摘要翻译：具有用于与左（205）和右（206）电子设备通信的左（203）和右（204）端口的存储设备（201）包括存储体（401-0〜401-7），信号量逻辑（302），和端口耦合电路（403,404,405-0〜405-7,406-0〜406-7,407-0〜407-7）。信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号（313,314），并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口银行存取授权信号。内存中还包括邮箱寄存器（2500-0L〜2500-3L，2500-0R〜2500-3R），中断发生电路（2514-0L〜2514-3L，2514-0R〜2514-3R，2900 ，3000,307,308），以及中断状态和原因寄存器（3101L〜3102L，3101R〜3102R，3301L〜3302L，3301R〜3302R）。左右电子设备使用邮箱寄存器相互发送消息，无需等待。中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备，并且当消息已被写入其中一个邮箱寄存器时。中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息，哪些邮箱寄存器包含用于它们的消息。

3. 发明授权

US5751638A Mail-box design for non-blocking communication across ports of a multi-port device 失效
标题翻译：用于多端口设备端口之间的非阻塞通信的邮箱设计
公开(公告)号：US5751638A
公开(公告)日：1998-05-12
申请号：US786401
申请日：1997-01-17
申请人： John Mick , Michael Miller , Jeff Smith , Mark Baumann
发明人： John Mick , Michael Miller , Jeff Smith , Mark Baumann
IPC分类号： G06F5/10 , G06F9/46 , G11C8/16 , G11C13/00
CPC分类号： G06F5/10 , G06F9/52 , G11C8/16
摘要： A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.
摘要翻译：具有用于与左（205）和右（206）电子设备进行通信的左（203）和右（204）端口的存储设备（201）包括存储体（401-0差分401-7），信号量逻辑（302），以及端口耦合电路（403,404,405-0，差异405-7,406-0，差异406-7,407-0，差异407-7）。信号量逻辑响应于来自左和右电子设备的存储体访问请求而在第一接收的基础上产生存储体存取授权信号（313,314），并且端口耦合电路响应于所选择的存储体耦合到左端口和右端口银行存取授权信号。存储设备中还包括邮箱寄存器（2500-0L DIFFERENCE 2500-3L，2500-0R差分2500-3R），中断产生电路（2514-0L差分2514-3L，2514-0R差分2514-3R，2900 ，3000,307,308）以及中断状态和原因寄存器（3101L差分3102L，3101R差分3102R，3301L差分3302L，3301R差分3302R）。左右电子设备使用邮箱寄存器相互发送消息，无需等待。中断产生电路产生中断以在其银行访问请求被授予时通知左和右电子设备，并且当消息已被写入其中一个邮箱寄存器时。中断状态和原因寄存器提供关于左和右电子设备被授权访问哪些存储器的信息，哪些邮箱寄存器包含用于它们的消息。

4. 发明授权

US08655162B2 Lens position based on focus scores of objects 有权
标题翻译：镜头位置基于焦点得分的对象
公开(公告)号：US08655162B2
公开(公告)日：2014-02-18
申请号：US13435820
申请日：2012-03-30
申请人： John Mick , Shane D Voss , Jason Yost
发明人： John Mick , Shane D Voss , Jason Yost
IPC分类号： G03B3/10 , G03B13/00
CPC分类号： G03B13/36 , H04N5/23212
摘要： Embodiments herein relate to setting a lens position based on focus scores. A plurality of initial positions of a lens are determined. Each of the initial positions may correspond to a position of the lens at which one of a plurality of objects has a highest quality. A focus score may be determined at each of the initial positions for the corresponding object having the highest quality. A final position of the lens between two of the initial positions may be calculated based on the focus scores.
摘要翻译：本文的实施例涉及基于焦点分数设置透镜位置。确定透镜的多个初始位置。每个初始位置可以对应于多个物体中的一个具有最高质量的透镜的位置。可以在具有最高质量的相应对象的每个初始位置处确定焦点得分。可以基于焦点得分来计算两个初始位置之间的透镜的最终位置。

5. 发明申请

US20050254330A1 Apparatus and method for matrix memory switching element 有权
标题翻译：矩阵存储器开关元件的装置和方法
公开(公告)号：US20050254330A1
公开(公告)日：2005-11-17
申请号：US11185072
申请日：2005-07-19
申请人： John Mick , Craig Lindahl , Yongdong Zhao
发明人： John Mick , Craig Lindahl , Yongdong Zhao
IPC分类号： H04L12/56 , G11C8/00
CPC分类号： H04L49/9036 , H04L47/568 , H04L47/6215 , H04L47/623 , H04L49/205 , H04L49/252 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90
摘要： A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.
摘要翻译：公开了一种包括输入端口和输出端口的矩阵式存储器阵列器件。每个输入端口耦合到第一数据总线，并且每个输出端口耦合到与第一数据总线不同且与第一数据总线分离的第二数据总线。存储砖被放置在第一数据总线和第二数据总线之间的每个交叉点处，以便可将数据帧从输入端口耦合到输出端口。每个存储砖包含多个八个晶体管（8-T）存储器单元，其可以用于存储，擦除，读取，写入和可切换地将数据位从输入端口耦合到相应的输出端口。

6. 发明申请

US20120154559A1 Generate Media 审中-公开
标题翻译：生成媒体
公开(公告)号：US20120154559A1
公开(公告)日：2012-06-21
申请号：US12974142
申请日：2010-12-21
申请人： Shane D. Voss , John Mick , Jason Yost
发明人： Shane D. Voss , John Mick , Jason Yost
IPC分类号： H04N13/00
CPC分类号： H04N13/398 , H04N13/327 , H04N13/341
摘要： A device to calibrate with a 3D viewer, to couple to a display device, and to split a 3D signal to a first 2D signal and a second 2D signal and generate media to be rendered on the display device by merging the first 2D signal and the second 2D signal based on a timing between the device and the 3D viewer.
摘要翻译：一种用3D查看器进行校准，耦合到显示设备，以及将3D信号分割为第一2D信号和第二2D信号的设备，并且通过将第一2D信号和第二2D信号合并并产生要在显示设备上渲染的介质基于设备和3D观看者之间的定时的第二2D信号。

7. 发明申请

US20070097254A1 Devices and methods for calculating pixel values representative of a scene 有权
标题翻译：用于计算表示场景的像素值的装置和方法
公开(公告)号：US20070097254A1
公开(公告)日：2007-05-03
申请号：US11262701
申请日：2005-10-31
申请人： Amy Battles , Jason Yost , John Mick
发明人： Amy Battles , Jason Yost , John Mick
IPC分类号： H04N5/238
CPC分类号： H04N5/2352 , H04N5/23293 , H04N5/2351
摘要： Methods of calculating pixel values representative of a scene are disclosed herein. One embodiment of the method comprises focusing light representative of the scene onto a photosensor for a period of time using at least one exposure setting, wherein the photosensor has a plurality of pixels. Numeric values corresponding to the intensity of light received by each of the pixels during the period are generated. At least one exposure setting is changed and pixel values are generated by the photosensor based on the changed at least one exposure setting are calculated. The number of calculated pixel values that are greater than a first preselected value are then determined.
摘要翻译：本文公开了计算代表场景的像素值的方法。该方法的一个实施例包括使用至少一个曝光设置将表示场景的光聚焦到光传感器一段时间，其中光传感器具有多个像素。生成与周期期间的每个像素接收的光的强度对应的数值。至少一个曝光设置被改变，并且基于改变的至少一个曝光设置由光传感器产生像素值。然后确定大于第一预选值的计算的像素值的数量。

8. 发明申请

US20060227761A1 Phone-based remote media system interaction 有权
公开(公告)号：US20060227761A1
公开(公告)日：2006-10-12
申请号：US11100758
申请日：2005-04-07
申请人： Samuel Scott , John Mick
发明人： Samuel Scott , John Mick
IPC分类号： H04L12/66
CPC分类号： H04L12/2803 , H04L12/2818 , H04M11/007 , H04N7/17318 , H04N21/2393 , H04N21/25875 , H04N21/4753 , H04N21/4788 , H04N21/6187
摘要： Phone-based remote media system interaction is described. A content distribution system provides a telephone-based voice menu system that enables a caller to select a media system control command. The content distribution system then causes the media system control command to be executed in association with a remote media system associated with, or specified by, the caller.

9. 发明申请

US20130286249A1 AUTOMATICALLY CAPTURING IMAGES THAT INCLUDE LIGHTNING 有权
标题翻译：自动拍摄包含闪电的图像
公开(公告)号：US20130286249A1
公开(公告)日：2013-10-31
申请号：US13456831
申请日：2012-04-26
申请人： Jason Yost , Shane D. Voss , John Mick
发明人： Jason Yost , Shane D. Voss , John Mick
IPC分类号： H04N5/225
CPC分类号： H04N5/232 , H04N5/772
摘要： A method is disclosed for capturing one or more images that include a lightning strike using an image capturing device. The method is performed by one or more processors of the image capturing device. The one or more processors automatically capture a plurality of images during a period of time using the lens of the device. Each of the plurality of images is processed to detect a presence of lightning within each image. Each image is processed based, at least part, on two consecutive captured images. Images that have been determined to include the presence of lightning are stored in a memory resource of the image capturing device.
摘要翻译：公开了一种用于捕获包括使用图像捕获装置的雷击的一个或多个图像的方法。该方法由图像捕获装置的一个或多个处理器执行。一个或多个处理器在使用该设备的镜头的一段时间期间自动地捕获多个图像。处理多个图像中的每一个以检测每个图像内的闪电的存在。每个图像至少部分地基于两个连续的拍摄图像进行处理。被确定为包括闪电存在的图像被存储在图像捕获装置的存储器资源中。

10. 发明授权

US07715377B2 Apparatus and method for matrix memory switching element 有权
标题翻译：矩阵存储器开关元件的装置和方法
公开(公告)号：US07715377B2
公开(公告)日：2010-05-11
申请号：US11185072
申请日：2005-07-19
申请人： John Mick , Craig Lindahl , Yongdong Zhao
发明人： John Mick , Craig Lindahl , Yongdong Zhao
IPC分类号： H04L12/56
CPC分类号： H04L49/9036 , H04L47/568 , H04L47/6215 , H04L47/623 , H04L49/205 , H04L49/252 , H04L49/30 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/90
摘要： A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.
摘要翻译：公开了一种包括输入端口和输出端口的矩阵式存储器阵列器件。每个输入端口耦合到第一数据总线，并且每个输出端口耦合到不同于第一数据总线的第二数据总线。存储砖被放置在第一数据总线和第二数据总线之间的每个交叉点处，以便可将数据帧从输入端口耦合到输出端口。每个存储砖包含多个八个晶体管（8-T）存储器单元，其可以用于存储，擦除，读取，写入和可切换地将数据位从输入端口耦合到相应的输出端口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式