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1. 发明申请

US20080016141A1 A DIRECT DIGITAL SYNTHESIS CIRCUIT 有权
标题翻译：直接数字合成电路
公开(公告)号：US20080016141A1
公开(公告)日：2008-01-17
申请号：US11457380
申请日：2006-07-13
申请人： Michael L. Bushman , Neal W. Hollenbeck , Patrick L. Rakers
发明人： Michael L. Bushman , Neal W. Hollenbeck , Patrick L. Rakers
IPC分类号： G06G7/16
CPC分类号： G06G7/26
摘要： A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.
摘要翻译：直接数字合成电路（108）包括多个电流源（210,211,212），输出电路（200）和逻辑乘法器电路（202）。输出电路（200）提供输出的合成波形（164），并包括第一分支（206）和第二分支（208）。逻辑乘法器电路（202）可操作地耦合到多个电流源（210,211,212）和输出电路（200）。逻辑乘法器电路（202）可操作以接收多个信号。逻辑乘法器电路还可操作以选择性地将通过第一分支（206）的第一电流流动增加确定的幅度，并且基于多个信号减少通过第二分支（208）的确定的幅度的第二电流。合成波形（164）基于第一和第二电流。

2. 发明授权

US07653678B2 Direct digital synthesis circuit 有权
标题翻译：直接数字合成电路
公开(公告)号：US07653678B2
公开(公告)日：2010-01-26
申请号：US11457380
申请日：2006-07-13
申请人： Michael L. Bushman , Neal W. Hollenbeck , Patrick L. Rakers
发明人： Michael L. Bushman , Neal W. Hollenbeck , Patrick L. Rakers
IPC分类号： G06G7/16
CPC分类号： G06G7/26
摘要： A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.
摘要翻译：直接数字合成电路（108）包括多个电流源（210,211,212），输出电路（200）和逻辑乘法器电路（202）。输出电路（200）提供输出的合成波形（164），并包括第一分支（206）和第二分支（208）。逻辑乘法器电路（202）可操作地耦合到多个电流源（210,211,212）和输出电路（200）。逻辑乘法器电路（202）可操作以接收多个信号。逻辑乘法器电路还可操作以选择性地将通过第一分支（206）的第一电流流过确定的幅度，并且基于多个信号减少通过第二分支（208）的确定的幅度的第二电流。合成波形（164）基于第一和第二电流。

3. 发明申请

US20080012628A1 A DUAL MODE VOLTAGE SUPPLY CIRCUIT 有权
标题翻译：双模电压供电电路
公开(公告)号：US20080012628A1
公开(公告)日：2008-01-17
申请号：US11457312
申请日：2006-07-13
申请人： Michael L. Bushman , James W. Caldwell , Neal W. Hollenbeck
发明人： Michael L. Bushman , James W. Caldwell , Neal W. Hollenbeck
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.
摘要翻译：双模式电压供给电路（50）包括有源模式电压供给电路（58）和被动模式电压供给电路（60）。主动模式电压供给电路（58）有选择地操作以基于模式控制信息（22）提供电压（57）。主动模式电压供应电路（58）可操作以提供第一电流容量。被动模式电压供应电路（60）可操作地耦合到有源模式电压供应电路（58）。当激活模式电压供应电路（58）不提供电压（57）时，被动模式电压供应电路（60）可操作地提供电压（57）。无源模式电压供应电路（60）可操作以提供小于第一电流容量的第二电流容量。

4. 发明授权

US07479824B2 Dual mode voltage supply circuit 有权
标题翻译：双模电源电路
公开(公告)号：US07479824B2
公开(公告)日：2009-01-20
申请号：US11457312
申请日：2006-07-13
申请人： Michael L. Bushman , James W. Caldwell , Neal W. Hollenbeck
发明人： Michael L. Bushman , James W. Caldwell , Neal W. Hollenbeck
IPC分类号： G05F1/46 , G05F3/08
CPC分类号： G05F1/56
摘要： A dual mode voltage supply circuit (50) includes an active mode voltage supply circuit (58) and a passive mode voltage supply circuit (60). The active mode voltage supply circuit (58) is selectively operative to supply a voltage (57) based on mode control information (22). The active mode voltage supply circuit (58) is operative to provide a first current capacity. The passive mode voltage supply circuit (60) is operatively coupled to the active mode voltage supply circuit (58). The passive mode voltage supply circuit (60) is operative to supply the voltage (57) when the active mode voltage supply circuit (58) is not supplying the voltage (57). The passive mode voltage supply circuit (60) is operative to provide a second current capacity that is less than the first current capacity.
摘要翻译：双模式电压供给电路（50）包括有源模式电压供给电路（58）和被动模式电压供给电路（60）。主动模式电压供给电路（58）有选择地操作以基于模式控制信息（22）提供电压（57）。主动模式电压供应电路（58）可操作以提供第一电流容量。被动模式电压供应电路（60）可操作地耦合到有源模式电压供应电路（58）。当激活模式电压供应电路（58）不提供电压（57）时，被动模式电压供应电路（60）可操作地提供电压（57）。无源模式电压供应电路（60）可操作以提供小于第一电流容量的第二电流容量。

5. 发明授权

US06763996B2 Method of communication in a radio frequency identification system 失效
标题翻译：射频识别系统中的通信方法
公开(公告)号：US06763996B2
公开(公告)日：2004-07-20
申请号：US09955345
申请日：2001-09-18
申请人： Patrick L. Rakers , Timothy James Collins , Richard Stanley Rachwalski , Michael L. Bushman
发明人： Patrick L. Rakers , Timothy James Collins , Richard Stanley Rachwalski , Michael L. Bushman
IPC分类号： G06F1700
CPC分类号： G06K19/0723 , G06K7/0008
摘要： In accordance with the present invention, a radio frequency identification (RFID) device comprises a plurality of data fields. The RFID device transmits a data symbol from a data field, receives an acknowledgement symbol, and compares the transmitted data symbol to the received acknowledgement symbol. The RFID device repeats these steps until data transmission is complete as long as each transmitted data symbol is equivalent to a corresponding received acknowledgement symbol; otherwise, the RFID device maintains the data field from which the last data symbol was transmitted, and temporarily suspends data transmission. When the RFID receives a request for RFID devices temporarily suspended in a given data field to resume data transmission, if the given data field in the request is equivalent to the data field that was maintained, the RFID device repeats the steps above starting with the first symbol in the data field that was maintained.
摘要翻译：根据本发明，射频识别（RFID）设备包括多个数据字段。 RFID设备从数据字段发送数据符号，接收确认符号，并将发送的数据符号与接收到的确认符号进行比较。 RFID设备重复这些步骤直到数据传输完成，只要每个发送的数据符号等同于相应的接收的确认符号; 否则，RFID设备维护发送最后一个数据符号的数据字段，并暂时暂停数据传输。当RFID接收到暂时停留在给定数据字段中的RFID设备的请求以恢复数据传输时，如果请求中的给定数据字段等同于维护的数据字段，则RFID设备重复上述步骤，从第一在维护的数据字段中的符号。

6. 发明授权

US5481229A Low power temperature compensated crystal oscillator 失效
标题翻译：低功耗温度补偿晶体振荡器
公开(公告)号：US5481229A
公开(公告)日：1996-01-02
申请号：US346452
申请日：1994-11-29
申请人： Lawrence E. Connell , Timothy J. Collins , Anthony F. Keller , Dennis F. Marvin , Michael L. Bushman
发明人： Lawrence E. Connell , Timothy J. Collins , Anthony F. Keller , Dennis F. Marvin , Michael L. Bushman
IPC分类号： H03L1/00 , H03B5/32 , H03L1/02
CPC分类号： H03L1/023
摘要： A temperature compensated crystal oscillator (10), has a crystal oscillator circuit (12), a voltage controlled reactance element (30), a temperature compensation network (50), and a programmable DC-DC converter network (60) having an output (62) connected to the voltage controlled reactance element (30), or the temperature compensation network (50) or both. The DC-DC converter network (60) provides the capability of operating over an extended voltage range, by increasing the supply voltage to a level necessary to operate the voltage controlled reactance element (30). Much of this structure is adapted for use in an integrated circuit, and provides the advantages of minimizing power and current consumption.
摘要翻译：温度补偿晶体振荡器（10）具有晶体振荡器电路（12），压控电抗元件（30），温度补偿网络（50）和可编程DC-DC转换器网络（60）连接到电压控制电抗元件（30）或温度补偿网络（50）或两者。 DC-DC转换器网络（60）通过将电源电压增加到操作电压控制电抗元件（30）所需的电平来提供在扩展电压范围上工作的能力。这种结构中的大部分适用于集成电路，并且提供最小化功率和电流消耗的优点。

7. 发明授权

US06657502B2 Multiphase voltage controlled oscillator 有权
标题翻译：多相压控振荡器
公开(公告)号：US06657502B2
公开(公告)日：2003-12-02
申请号：US09968171
申请日：2001-10-01
申请人： Michael L. Bushman , Lawrence E. Connell
发明人： Michael L. Bushman , Lawrence E. Connell
IPC分类号： H03B2700
CPC分类号： H03B27/00
摘要： A multiphase voltage controlled oscillator (e.g., a quadrature VCO) 100, which includes multiple voltage controllable transconductance phase drivers 102, 104, 106 and 108. The output of each voltage controllable transconductance phase driver 102, 104, 106, 108 supplies one of 4 oscillator phases and receives 2 of the 4 phases as inputs. Each of the voltage controllable transconductance phase drivers 102, 104, 106 and 108 corresponds to a pair of controllable transconductance inverting amplifiers 132, 134, 136, 138. The controllable transconductance inverting amplifiers may be a simple inverter 150 that includes N-type FET (NFET) 152 and P-type FET (PFET) 154. Transconductance is controlled in the simple inverter by raising or lowering supply voltage (Vdd) levels. A more complex controllable transconductance inverting amplifier may be used, replacing PFET 154 with series connected PFETs 164, 166. The gate of one PFET 166 is controlled by a bias control voltage VCON. For additional sensitivity and control PFETs 164, 166 may each be replaced with parallel pairs of PFETs 174, 176 and 178, 180. In addition to a quadrature VCO, an N phase oscillator may be formed with each phase generated by a controllable transconductance functional block, appropriately selecting block inputs from output phases.
摘要翻译：多相压控振荡器（例如，正交VCO）100，其包括多个电压可控跨导相位驱动器102,104,106和108.每个电压可控跨导相位驱动器102,104,106,108的输出提供4个振荡器相位，并接收4相中的2个作为输入。电压可控跨导相位驱动器102,104,106和108中的每一个对应于一对可控跨导反相放大器132,134,136,138。可控跨导反相放大器可以是简单的反相器150，其包括N型FET（ NFET）152和P型FET（PFET）154.通过升高或降低电源电压（Vdd）电平，在简单的逆变器中控制跨导。可以使用更复杂的可控跨导反相放大器，用串联的PFET 164,166代替PFET154.一个PFET 166的栅极由偏置控制电压VCON控制。对于额外的灵敏度和控制，PFET 164,166可以各自被平行的PFET 174,176和178,180所代替。除了正交VCO之外，可以形成N相振荡器，每个相由可控的跨导功能块，从输出阶段适当地选择块输入。

8. 发明授权

US5764111A Voltage controlled ring oscillator frequency multiplier 失效
标题翻译：压控环振荡器倍频器
公开(公告)号：US5764111A
公开(公告)日：1998-06-09
申请号：US801444
申请日：1997-02-18
申请人： Michael L. Bushman
发明人： Michael L. Bushman
IPC分类号： H03K3/03 , H03L7/099 , H03L7/16 , H03L7/183 , H03B27/00
CPC分类号： H03K3/0315 , H03L7/0995 , H03L7/16 , H03L2207/10 , H03L7/183
摘要： A voltage controlled ring oscillator (10) integrated with a phase locked loop (101) using CMOS technology. The ring oscillator (10) provides a frequency multiplied harmonic output frequency (42) at a frequency of 2.5 GHz or more while operating at only one-third of that frequency. The ring oscillator (10) uses an odd number of inverter stages (12, 14, 16) and provides high frequency CMOS operation by utilizing the phase shifted signals of the ring frequency at each ring inverter output (20, 24, 28). The ring oscillator (10) draws minimal current and is incorporated in a frequency synthesizer (100) used in a radio communication device (200).
摘要翻译：使用CMOS技术与锁相环（101）集成的压控环形振荡器（10）。环形振荡器（10）以2.5GHz或更高的频率提供倍频谐波输出频率（42），同时仅在该频率的三分之一处工作。环形振荡器（10）使用奇数个反相器级（12,14,16），并且通过利用每个环形反相器输出（20,24,28）处的环形频率的相移信号来提供高频CMOS操作。环形振荡器（10）吸收最小的电流，并且被并入在无线电通信装置（200）中使用的频率合成器（100）中。

9. 发明授权

US5414354A Apparatus and method for generating a substantially rectangular output signal 失效
标题翻译：用于产生大致矩形输出信号的装置和方法
公开(公告)号：US5414354A
公开(公告)日：1995-05-09
申请号：US103843
申请日：1993-08-09
申请人： Michael L. Bushman , Kenneth C. Fuchs
发明人： Michael L. Bushman , Kenneth C. Fuchs
IPC分类号： H03K5/003 , H03K5/12 , H03K5/156 , H03K12/00
CPC分类号： H03K5/003 , H03K5/12 , H03K5/1565
摘要： A squaring amplifier circuit (300) generates a substantially rectangular output signal from an a.c. input signal. An amplifier stage (303) is biased at a low quiescent current by a current source network (305) and a coupling network (306). Since the amplifier stage (303) current is a non-linear function of its input voltage, application of a low-level a.c. input signal (313), through an input signal coupling network (302), results in a substantially rectangular output signal having frequency and duty cycle that are substantially identical to the frequency and duty cycle of the input signal.
摘要翻译：平方放大器电路（300）从交流电源（300）产生基本矩形的输出信号。输入信号。放大器级（303）由电流源网络（305）和耦合网络（306）偏置在低静态电流。由于放大器级（303）的电流是其输入电压的非线性函数，因此应用低电平电流。输入信号（313）通过输入信号耦合网络（302）产生具有基本上与输入信号的频率和占空比相同的频率和占空比的基本上矩形的输出信号。

10. 发明授权

US07332979B2 Low noise reference oscillator with fast start-up 有权
标题翻译：低噪声基准振荡器，启动速度快
公开(公告)号：US07332979B2
公开(公告)日：2008-02-19
申请号：US11261978
申请日：2005-10-28
申请人： Lawrence E. Connell , Daniel P. McCarthy , Michael L. Bushman
发明人： Lawrence E. Connell , Daniel P. McCarthy , Michael L. Bushman
IPC分类号： H03B5/36
CPC分类号： H03L3/00 , H03B5/06 , H03L5/00
摘要： A frequency source having a fast start-up time and low noise in steady state is presented. The frequency source includes an oscillator and a hybrid automatic gain control (AGC) loop that switches between an analog AGC loop at oscillator start up and a digital AGC loop at steady state operation. The analog AGC loop includes a peak detector connected to the oscillator and an error integrator integrating the difference between the peak detector output and a reference voltage. The digital AGC loop includes a comparator comparing the peak detector output and high/low reference voltages, an oscillator counter providing a timer signal, a digital-to-analog converter (DAC) supplied with a digital word, and a low pass filter between the DAC and the oscillator. The timer signal causes a multiplexer to select either the analog AGC loop or the digital AGC loop.
摘要翻译：提出了一种在稳态下具有快速起动时间和低噪声的频率源。频率源包括振荡器和混合自动增益控制（AGC）环路，其在振荡器启动时在模拟AGC环路和稳态操作之间的数字AGC环路之间切换。模拟AGC环路包括连接到振荡器的峰值检测器和积分峰值检测器输出和参考电压之间的差的误差积分器。数字AGC环路包括比较峰值检测器输出和高/低参考电压的比较器，提供定时器信号的振荡器计数器，提供有数字字的数模转换器（DAC）和在数字字之间的低通滤波器 DAC和振荡器。定时器信号使多路复用器选择模拟AGC环路或数字AGC环路。

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