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1. 发明申请

US20070192577A1 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment 有权
标题翻译：在多处理器环境中单方面加载安全操作系统的装置和方法
公开(公告)号：US20070192577A1
公开(公告)日：2007-08-16
申请号：US11340181
申请日：2006-01-24
申请人： Michael Kozuch , James Sutton , David Grawrock , Gilbert Neiger , Richard Uhlig , Bradley Burgess , David Poisner , Clifford Hall , Andy Glew , Lawrence Smith , Robert George
发明人： Michael Kozuch , James Sutton , David Grawrock , Gilbert Neiger , Richard Uhlig , Bradley Burgess , David Poisner , Clifford Hall , Andy Glew , Lawrence Smith , Robert George
IPC分类号： G06F15/177
CPC分类号： G06F21/57
摘要： An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.
摘要翻译：描述了在多处理器环境内单方面加载安全操作系统的装置和方法。该方法包括当检测到当前活动的负载安全区域操作时忽略接收到的负载安全区域指令。否则，响应于接收到的负载安全区域指令，引导存储器保护元件以形成安全存储器环境。一旦定向，就禁止对一个或多个受保护的存储器区域进行未经授权的读/写访问。最后，一个或多个受保护的存储器区域的加密散列值作为安全的软件识别值存储在摘要信息库中。一旦存储，外部代理可以请求访问数字签名的软件标识值以建立安全存储器环境内的安全软件的安全验证。

2. 发明申请

US20120059971A1 METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOAD FORWARDING 审中-公开
标题翻译：用于处理存储到负载转向的关键阻塞的方法和装置
公开(公告)号：US20120059971A1
公开(公告)日：2012-03-08
申请号：US12876912
申请日：2010-09-07
申请人： DAVID KAPLAN , Tarun Nakra , Christopher D. Bryant , Bradley Burgess
发明人： DAVID KAPLAN , Tarun Nakra , Christopher D. Bryant , Bradley Burgess
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0804 , G06F9/3834 , G06F12/0897 , G06F12/1027 , G06F2212/502
摘要： The present invention provides a method and apparatus for handling critical blocking of store-to-load forwarding. One embodiment of the method includes recording a load that matches an address of a store in a store queue before the store has valid data. The load is blocked because the store does not have valid data. The method also includes replaying the load in response to the store receiving valid data so that the valid data is forwarded from the store queue to the load.
摘要翻译：本发明提供了一种用于处理存储到负载转发的关键阻塞的方法和装置。该方法的一个实施例包括在商店具有有效数据之前记录与存储队列中的商店的地址匹配的负载。由于存储没有有效的数据，所以加载被阻止。该方法还包括响应于存储器接收有效数据重放负载，使得有效数据从存储队列转发到负载。

3. 发明授权

US5642493A Method of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instruction 失效
标题翻译：通过重复使用包含错误预测的分支指令的例程将指令加载到指令高速缓存中的方法
公开(公告)号：US5642493A
公开(公告)日：1997-06-24
申请号：US345043
申请日：1994-11-25
申请人： Bradley Burgess
发明人： Bradley Burgess
IPC分类号： G06F9/38 , G06F12/08 , G06F12/06
CPC分类号： G06F9/3802 , G06F12/0875 , G06F9/3846 , G06F12/0862
摘要： A method of loading a particular block of instructions into the instruction cache (14) of a Harvard architecture data processor (10) involves repetitively mis-predicting a branch instruction in a loop. The branch instruction is conditioned upon an instruction whose execution is contrived to output a sequential fetch address. However, the instruction's result is not available until after the branch instruction begins executing. Therefore, the data processor speculatively executes or predicts the branch instruction. In this case, the branch instruction predicts that it will branch to the particular block of instructions. The data processor then loads the instructions into its instruction cache. Later, the data processor determines that it mis-predicted the branch instruction, returning to the loop for another iteration.
摘要翻译：将特定指令块加载到哈佛架构数据处理器（10）的指令高速缓存（14）中的方法涉及重复地错误地预测循环中的分支指令。分支指令基于执行被输出以输出顺序取出地址的指令。但是，在分支指令开始执行之后，指令的结果是不可用的。因此，数据处理器推测地执行或预测分支指令。在这种情况下，分支指令预测它将分支到特定的指令块。然后，数据处理器将指令加载到其指令高速缓存中。之后，数据处理器确定它错误地预测了分支指令，返回到循环进行另一次迭代。

4. 发明授权

US5408428A Programmable bit cell 失效
标题翻译：可编程位单元
公开(公告)号：US5408428A
公开(公告)日：1995-04-18
申请号：US176811
申请日：1994-01-03
申请人： Bradley Burgess , Jeffrey Slaton
发明人： Bradley Burgess , Jeffrey Slaton
IPC分类号： G11C17/10 , H01L27/02 , G11C17/00
CPC分类号： H01L23/544 , G11C17/10 , H01L2223/5444 , H01L2223/54473 , H01L27/02 , H01L2924/0002
摘要： A mask-programmable read only memory bit cell (16) has a pair of conductive elements for each conductive layer in the integrated device but the last layer (30 and 34, 38 and 42, 46 and 50) and single conductive element in the last layer (54). The first and second elements in the first pair of elements receive a first and a second voltage supply (V.sub.DD and V.sub.GND), respectively. The single element outputs a voltage corresponding to the logic state stored by the bit cell. A plurality of pairs of conductive vias couple particular ones of the elements in each layer to particular ones of the elements in adjacent layers. The logic state stored by the bit cell may be reversed by reversing the connection of any one pair of elements and its associated vias. This makes the bit cell suitable for use in a processor version register.
摘要翻译：掩模可编程只读存储器位单元（16）具有用于集成器件中的每个导电层的一对导电元件，但是最后一层（30和34,38,42,46和50）和最后一层中的单个导电元件层（54）。第一对元件中的第一和第二元件分别接收第一和第二电压源（VDD和VGND）。单个元件输出与位单元存储的逻辑状态对应的电压。多对导电通孔将每个层中的特定元件与相邻层中的特定元件相结合。由位单元存储的逻辑状态可以通过反转任何一对元件及其相关联的通孔的连接来反转。这使得位单元适用于处理器版本寄存器。

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