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1. 发明申请

US20050170193A1 Process for modifying polymeric surfaces using deep UV irradiation 失效
标题翻译：使用深紫外线照射改性聚合物表面的方法
公开(公告)号：US20050170193A1
公开(公告)日：2005-08-04
申请号：US11047939
申请日：2005-02-01
申请人： Michael Kelley , Zhengmao Zhu
发明人： Michael Kelley , Zhengmao Zhu
IPC分类号： A01N25/34 , B05D3/00 , B32B27/16 , B32B27/36 , C08J7/18
CPC分类号： A01N25/34 , C08J7/18 , D06M10/001 , D06M10/08 , D06M14/32 , D06M16/00 , Y10T428/31536 , Y10T428/31786 , A01N59/16 , A01N33/12 , A01N25/10
摘要： A process is described for modifying polymeric surfaces. The process is particularly useful for modification of polyesters, and can be used to impart surface functionality that confers antimicrobial, anti-soiling, or other desirable properties to the polymer. The process comprises the steps of exposing a polymeric substrate to deep UV irradiation, followed by reaction with a grafting agent. In preferred embodiments, a vapor-phase grafting agent undergoes covalent reactions with the UV-modified polymer surface to produce a polymer with improved properties.
摘要翻译：描述了用于改性聚合物表面的方法。该方法对聚酯的改性特别有用，并且可用于赋予聚合物赋予抗微生物，抗污染或其它所需性质的表面官能团。该方法包括以下步骤：将聚合物基材暴露于深紫外线照射，随后与接枝剂反应。在优选的实施方案中，气相接枝剂与UV改性的聚合物表面发生共价反应以产生具有改进性能的聚合物。

2. 发明申请

US20110241597A1 H-BRIDGE DRIVE CIRCUIT FOR STEP MOTOR CONTROL 审中-公开
标题翻译：用于步进电机控制的H型桥式驱动电路
公开(公告)号：US20110241597A1
公开(公告)日：2011-10-06
申请号：US12750454
申请日：2010-03-30
申请人： Zhengmao Zhu , Jongwon Kim , Kayvan Abbassian
发明人： Zhengmao Zhu , Jongwon Kim , Kayvan Abbassian
IPC分类号： H02P8/14
CPC分类号： H02P8/12 , H02P8/16
摘要： A drive circuit for step motors with bifilar windings is provided in which both parallel and series winding configurations for the stator coils are selectable by a motor controller based on the motor speed. For low speeds a series configuration is selected, while for higher speeds a parallel configuration is selected. Dynamic torque is optimized by the selection for more efficient motor operation with less drive current.
摘要翻译：提供了具有双线绕组的步进电动机的驱动电路，其中定子线圈的并联绕组和串联绕组配置可以由马达控制器基于电机速度来选择。对于低速度，选择串联配置，而对于较高速度，选择并联配置。通过选择更有效的电机运行来优化动态转矩，减少驱动电流。

3. 发明申请

US20120248436A1 REDUCED PATTERN LOADING FOR DOPED EPITAXIAL PROCESS AND SEMICONDUCTOR STRUCTURE 失效
标题翻译：用于掺杂外延工艺和半导体结构的减少图案加载
公开(公告)号：US20120248436A1
公开(公告)日：2012-10-04
申请号：US13075450
申请日：2011-03-30
申请人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
发明人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
IPC分类号： H01L23/48 , H01L21/20
CPC分类号： H01L21/823425 , H01L21/02529 , H01L21/02576 , H01L21/823412 , H01L22/12 , H01L22/34 , H01L29/66636 , H01L29/7848
摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.
摘要翻译：提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

4. 发明申请

US20120086071A1 STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE 有权
标题翻译：应力记忆过程改进改进的技术性能
公开(公告)号：US20120086071A1
公开(公告)日：2012-04-12
申请号：US12902624
申请日：2010-10-12
申请人： Lahir Shaik Adam , Bruce B. Doris , Sanjay Mehta , Zhengmao Zhu
发明人： Lahir Shaik Adam , Bruce B. Doris , Sanjay Mehta , Zhengmao Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7847
摘要： Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.
摘要翻译：具有变形栅极区域的半导体衬底及其制造方法。与具有变形的源极/漏极区域的器件相比，半导体衬底与不具有变形栅极区域的器件相比具有改进的器件性能和降低的掺杂剂损耗。

5. 发明授权

US08035141B2 Bi-layer nFET embedded stressor element and integration to enhance drive current 有权
标题翻译：双层nFET嵌入式应力元件并集成增强驱动电流
公开(公告)号：US08035141B2
公开(公告)日：2011-10-11
申请号：US12607104
申请日：2009-10-28
申请人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

6. 发明授权

US09059292B2 Source and drain doping profile control employing carbon-doped semiconductor material 有权
标题翻译：使用碳掺杂半导体材料的源极和漏极掺杂分布控制
公开(公告)号：US09059292B2
公开(公告)日：2015-06-16
申请号：US13564862
申请日：2012-08-02
申请人： Viorel Ontalus , Pranita Kulkarni , Donald R. Wall , Zhengmao Zhu
发明人： Viorel Ontalus , Pranita Kulkarni , Donald R. Wall , Zhengmao Zhu
IPC分类号： H01L29/02 , H01L29/786 , H01L29/66 , H01L29/08 , H01L29/165 , H01L29/417 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/823412 , H01L29/0649 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7834 , H01L29/78618 , H01L29/78687 , H01L2029/7858
摘要： Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.
摘要翻译：碳掺杂半导体材料部分形成在与场效应晶体管的沟道连接的下面的半导体表面的子集上。碳掺杂半导体材料部分可以通过含碳半导体材料层的选择性外延或通过将碳原子浅入注入下面的半导体表面的表面部分来形成。碳掺杂的半导体材料部分可以作为层沉积，然后通过蚀刻进行图案化，或者可以在形成一次性掩模间隔物之后形成。在碳掺杂的半导体材料部分和下面的半导体表面的物理暴露的表面上形成凸起的源区和漏区。碳掺杂半导体材料部分将掺杂剂扩散部分局部延迟从升高的源极和漏极区域延伸到下面的半导体材料区域中，从而使得能够局部定制掺杂剂分布，以及改变场效应晶体管的器件参数。

7. 发明授权

US08421191B2 Monolayer dopant embedded stressor for advanced CMOS 有权
标题翻译：单层掺杂剂嵌入式应力器用于高级CMOS
公开(公告)号：US08421191B2
公开(公告)日：2013-04-16
申请号：US13533499
申请日：2012-06-26
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L31/117
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
摘要翻译：公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

8. 发明授权

US08338279B2 Reduced pattern loading for doped epitaxial process and semiconductor structure 失效
标题翻译：用于掺杂外延工艺和半导体结构的减少图案负载
公开(公告)号：US08338279B2
公开(公告)日：2012-12-25
申请号：US13075450
申请日：2011-03-30
申请人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
发明人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
IPC分类号： H01L21/20
CPC分类号： H01L21/823425 , H01L21/02529 , H01L21/02576 , H01L21/823412 , H01L22/12 , H01L22/34 , H01L29/66636 , H01L29/7848
摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.
摘要翻译：提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

9. 发明申请

US20110095343A1 BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT 有权
标题翻译：双层NFET嵌入式应力元件和集成以增强驱动电流
公开(公告)号：US20110095343A1
公开(公告)日：2011-04-28
申请号：US12607104
申请日：2009-10-28
申请人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

10. 发明授权

US07585550B2 Process for modifying polymeric surfaces using deep UV irradiation 失效
标题翻译：使用深紫外线照射改性聚合物表面的方法
公开(公告)号：US07585550B2
公开(公告)日：2009-09-08
申请号：US11047939
申请日：2005-02-01
申请人： Michael J Kelley , Zhengmao Zhu
发明人： Michael J Kelley , Zhengmao Zhu
IPC分类号： C08J7/18
CPC分类号： A01N25/34 , C08J7/18 , D06M10/001 , D06M10/08 , D06M14/32 , D06M16/00 , Y10T428/31536 , Y10T428/31786 , A01N59/16 , A01N33/12 , A01N25/10
摘要： A process is described for modifying polymeric surfaces. The process is particularly useful for modification of polyesters, and can be used to impart surface functionality that confers antimicrobial, anti-soiling, or other desirable properties to the polymer. The process comprises the steps of exposing a polymeric substrate to deep UV irradiation, followed by reaction with a grafting agent. In preferred embodiments, a vapor-phase grafting agent undergoes covalent reactions with the UV-modified polymer surface to produce a polymer with improved properties.
摘要翻译：描述了用于改性聚合物表面的方法。该方法对聚酯的改性特别有用，并且可用于赋予聚合物赋予抗微生物，抗污染或其它所需性质的表面官能团。该方法包括以下步骤：将聚合物基材暴露于深紫外线照射，随后与接枝剂反应。在优选的实施方案中，气相接枝剂与UV改性的聚合物表面发生共价反应以产生具有改进性能的聚合物。

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