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1. 发明授权

US5923512A Fault tolerant circuit arrangements 失效
标题翻译：容错电路布置
公开(公告)号：US5923512A
公开(公告)日：1999-07-13
申请号：US41394
申请日：1998-03-12
申请人： Michael James Brownlow , Andrew Kay , Graham Andrew Cairns , Toshio Nomura
发明人： Michael James Brownlow , Andrew Kay , Graham Andrew Cairns , Toshio Nomura
IPC分类号： G01R31/00 , G02F1/133 , G06F11/07 , G09G3/20 , G09G3/36 , H02H3/18
CPC分类号： G06F11/2215 , H03K19/00392
摘要： A fault tolerant circuit arrangement comprises a plurality of replicated non-redundant shift registers 30 connected in parallel and each having an enable/configuration input 31 and a plurality of outputs 36. Furthermore each register 30 includes a verify output 32 for outputting a verify signal indicating whether or not a fault condition is present within the register. The arrangement also includes a verification signal generator 33 for applying a fixed reference signal, a comparator 34 to which the verify signals from the outputs 32 are applied, and a control circuit 35. The test/control-logic of the comparator 34 and control circuit 35 is constructed using masking redundancy 20-24 in order to render the test/control logic tolerant to faults. The control circuit 35 serves to control testing of each of the registers 30 in turn by supplying an enable signal to the input 31 of each register 30 beginning with the first register. This causes the supply of a verify signal V.sub.1 from the verify output 32 of the first register 30 to the comparator 34 which compares the verify signal V.sub.1 to the reference signal. If the verify signal V.sub.1 is significantly different from the reference signal, this indicates that there is a fault present in the first register, and the control circuit 35 is caused to supply a disable signal to the input 31 of the first register. The test procedure is repeated for each register 30 until a verify signal is received by the comparator 34 which indicates that there is no fault present in the associated register.
摘要翻译：容错电路装置包括并联连接的多个复制非冗余移位寄存器30，每一个具有使能/配置输入31和多个输出36.此外，每个寄存器30包括验证输出32，用于输出指示无论寄存器内是否存在故障状况。该装置还包括用于施加固定参考信号的验证信号发生器33，来自输出端32的验证信号的施加的比较器34以及控制电路35.比较器34和控制电路的测试/控制逻辑 35使用掩蔽冗余20-24构造，以便使测试/控制逻辑容忍故障。控制电路35用于依次通过从第一寄存器开始向每个寄存器30的输入端31提供使能信号来控制每个寄存器30的测试。这导致将验证信号V1从第一寄存器30的验证输出32提供给比较器34，比较器34将验证信号V1与参考信号进行比较。如果验证信号V1与参考信号显着不同，则表示第一寄存器中存在故障，并且使控制电路35向第一寄存器的输入端31提供禁止信号。对于每个寄存器30重复测试程序，直到比较器34接收到验证信号，其指示相关联的寄存器中不存在故障。

2. 发明授权

US06437767B1 Active matrix devices 失效
标题翻译：主动矩阵设备
公开(公告)号：US06437767B1
公开(公告)日：2002-08-20
申请号：US09054949
申请日：1998-04-03
申请人： Graham Andrew Cairns , Michael James Brownlow , Andrew Kay
发明人： Graham Andrew Cairns , Michael James Brownlow , Andrew Kay
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/3666
摘要： An active matrix device includes a data line driver circuit for sampling the input signal to produce data signals for each of the rows of control elements in a corresponding line period, and a scan line driver circuit for addressing the scan lines sequentially by applying a scan signal to the scan inputs of the control elements along each of the rows so as to supply said data signals to the control elements along the row. Such circuits are controlled so that a data input signal is sampled and stored to produce data signals for a first group of the control elements along the row in a first line subperiod and the stored data signals are applied to the first group of control elements in a second line subperiod, and so that the data input signal is sampled and stored to produce data signals for a second group of control elements along the row in the second line subperiod and the stored data signals are applied to the second group of control elements in a subsequent line subperiod.
摘要翻译：有源矩阵装置包括数据线驱动器电路，用于对输入信号进行采样，以在相应的行周期内为每行控制元件产生数据信号;以及扫描线驱动电路，用于通过施加扫描信号来顺序寻址扫描线到沿着每行的控制元件的扫描输入，以便将所述数据信号提供给沿着该行的控制元件。这样的电路被控制，使得数据输入信号被采样和存储，以产生沿着第一行子周期中的行的第一组控制元件的数据信号，并且存储的数据信号被施加到第一组控制元件并且使得数据输入信号被采样和存储以产生沿着第二行次周期中的行的第二组控制元件的数据信号，并且将存储的数据信号施加到第二组控制元件后续行周期

3. 发明授权

US6060941A Fault tolerant circuit arrangement and active matrix device incorporating the same 失效
标题翻译：容错电路布置和包含其的有源矩阵器件
公开(公告)号：US6060941A
公开(公告)日：2000-05-09
申请号：US37909
申请日：1998-03-10
申请人： Michael James Brownlow , Andrew Kay , Graham Andrew Cairns
发明人： Michael James Brownlow , Andrew Kay , Graham Andrew Cairns
IPC分类号： G02F1/136 , G02F1/1368 , G09F9/00 , G09G3/20 , G09G3/36 , G06F11/16
CPC分类号： G09G3/3688 , G09G2330/08
摘要： A fault tolerant circuit arrangement includes: an input; an output; a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element, provided in such a manner that the first and second circuit elements are connected in series between the input and the output to form a first series combination, and the third and fourth circuit elements are connected in series between the input and the output to form a second series combination, the first series combination being connected in parallel with the second series combination between the input and the output; and, a control element connected between an interconnection point of the first and second circuit elements and an interconnection point of the third and fourth circuit elements. The control element is switchable by a control signal between a conducting mode in which current flow is enabled between the interconnection points and a non-conducting mode in which current flow is prevented between the interconnection points.
摘要翻译：容错电路布置包括：输入; 输出第一电路元件，第二电路元件，第三电路元件和第四电路元件，其设置成使得第一和第二电路元件串联连接在输入和输出之间以形成第一串联组合，并且第三和第四电路元件串联在输入和输出之间以形成第二串联组合，第一串联组合与输入和输出之间的第二串联组合并联连接; 以及连接在第一和第二电路元件的互连点与第三和第四电路元件的互连点之间的控制元件。控制元件可通过控制信号切换，该控制信号在互连点之间启用电流的导通模式与在互连点之间防止电流流动的非导通模式之间。

4. 发明授权

US06268841B1 Data line driver for a matrix display and a matrix display 失效
标题翻译：用于矩阵显示和矩阵显示的数据线驱动
公开(公告)号：US06268841B1
公开(公告)日：2001-07-31
申请号：US09226737
申请日：1999-01-07
申请人： Graham Andrew Cairns , Michael James Brownlow , Andrew Kay
发明人： Graham Andrew Cairns , Michael James Brownlow , Andrew Kay
IPC分类号： G09G336
CPC分类号： G09G3/2011 , G09G3/3666 , G09G3/3688 , G09G3/3692 , G09G2310/027 , G09G2310/0294 , G09G2310/0297
摘要： A data line driver is provided for driving M data lines of a matrix display such as a liquid crystal display. The driver comprises x data line circuits whose inputs are connected to a common input for receiving a serial image signal, where x is less than M. Each of the data line circuits comprises a store for storing one picture element of image data at a time, a multiplexer for storing in the store in sequence image data for m picture elements from at least part of a line of image data, where m is greater than one, and a demultiplexer for directing a line signal corresponding to the image data stored in the store to each of m of the M data lines in sequence.
摘要翻译：提供数据线驱动器，用于驱动诸如液晶显示器的矩阵显示器的M个数据线。驱动器包括x个数据线电路，其输入端连接到用于接收串行图像信号的公共输入，其中x小于M.每个数据线电路包括一次存储一个图像数据的图像元素的存储器，一个多路复用器，用于从m个大于1的图像数据行的至少一部分存储用于m个图像元素的序列图像数据;多路分解器，用于引导与存储在存储器中的图像数据相对应的线信号 M个数据线的m个顺序。

5. 发明授权

US06232946B1 Active matrix drive circuits 失效
标题翻译：有源矩阵驱动电路
公开(公告)号：US06232946B1
公开(公告)日：2001-05-15
申请号：US09055083
申请日：1998-04-03
申请人： Michael James Brownlow , Graham Andrew Cairns , Andrew Kay
发明人： Michael James Brownlow , Graham Andrew Cairns , Andrew Kay
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , H03M1/667 , H03M1/68
摘要： A data line driver circuit for an active matrix liquid crystal display comprises a distributed controller in the form of a control shift register comprising a chain of control DFF's and associated detection logic. Furthermore the drive circuit includes a respective driver stage under the control of each control DFF for sampling the n-bit digital input signal and for supplying a drive signal to a corresponding data line. Each of the driver stages incorporates an n-bit vertically connected sample shift register composed of DFF's and associated 2:1 multiplexers which are used to provide an input either from the relevant bit line of the n-bit input data bus or from the output of the preceding DFF. In operation the n-bits of the input signal are supplied in parallel to the n inputs of the DFF's in a sampling mode, and the n-bits are shifted along the sample shift register towards the output of the shift register in a shifting mode. A serial D/A converter receives the n-bits sequentially and produces an analogue drive signal for driving the data line.
摘要翻译：用于有源矩阵液晶显示器的数据线驱动电路包括一个分布式控制器，其形式为控制移位寄存器，该控制移位寄存器包括一个控制链DFF和相关检测逻辑。此外，驱动电路在每个控制DFF的控制下包括相应的驱动级，用于对n位数字输入信号进行采样，并将驱动信号提供给相应的数据线。每个驱动级包括一个n位垂直连接的采样移位寄存器，由DFF和相关的2：1复用器组成，用于从n位输入数据总线的相关位线或从n位输入数据总线的输出前面的DFF。在操作中，输入信号的n位以采样模式并行提供给DFF的n个输入端，并且n位在移位模式下沿着采样移位寄存器移位到移位寄存器的输出端。串行D / A转换器顺序接收n位，并产生用于驱动数据线的模拟驱动信号。

6. 发明授权

US08354990B2 Drive circuit, a display device provided with the same 有权
标题翻译：驱动电路，具有该驱动电路的显示装置
公开(公告)号：US08354990B2
公开(公告)日：2013-01-15
申请号：US12087870
申请日：2007-01-29
申请人： Gareth John , Patrick Zebedee , Michael James Brownlow , Tim Gasser , Jeremy Lock , Graham Andrew Cairns , Jaganath Rajendra , Harry Garth Walton
发明人： Gareth John , Patrick Zebedee , Michael James Brownlow , Tim Gasser , Jeremy Lock , Graham Andrew Cairns , Jaganath Rajendra , Harry Garth Walton
IPC分类号： G09G3/36
CPC分类号： H03K17/063 , G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , G11C19/184
摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.
摘要翻译：在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路。每个升压电路连接在第一电压源和第二电压源之间。逻辑块可以是但不限于移位寄存器。

7. 发明授权

US07042433B1 Signal line driving circuit and image display device 有权
标题翻译：信号线驱动电路和图像显示装置
公开(公告)号：US07042433B1
公开(公告)日：2006-05-09
申请号：US09567364
申请日：2000-05-09
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Andrew Cairns , Michael James Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.
摘要翻译：信号线驱动电路包括具有多个移位电路的移位寄存器，每个移位电路将开始脉冲连续地移位到下一级，与时钟信号的定时同步。在该信号线驱动电路中，基于两个相邻移位电路的输出脉冲，从与门输出移位脉冲。同时，用于指定移位脉冲的脉冲宽度的宽度指定脉冲通过由移位脉冲控制其ON / OFF操作的晶体管输入。逻辑运算电路对移位脉冲和宽度指定脉冲进行AND运算，并将运算结果输出到信号线。当移位脉冲不起作用时，晶体管变为截止，使得将信号线发送宽度指定脉冲与信号线驱动电路断开，从而降低布线的容性负载。结果，实现了信号线驱动电路中布线的寄生电容的减小，元件数目的减少，输入信号的幅度的减小等。

8. 发明授权

US06970163B2 Frame rate controller 有权
标题翻译：帧速率控制器
公开(公告)号：US06970163B2
公开(公告)日：2005-11-29
申请号：US10092372
申请日：2002-03-05
申请人： Graham Andrew Cairns , Michael James Brownlow
发明人： Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00 , G09G5/18
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/006 , G09G5/18 , G09G2300/0408 , G09G2320/0276 , G09G2320/103 , G09G2330/021 , G09G2330/022 , G09G2340/0435
摘要： A frame rate controller (20) is provided for controlling the frame refresh rate of an active matrix display. The controller (20) comprises a first circuit such as a preloadable synchronous counter (21) which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement (26) is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.
摘要翻译：提供了一种用于控制有源矩阵显示器的帧刷新率的帧速率控制器（20）。控制器（20）包括第一电路，例如对可垂直同步信号VSYNC进行计数的预加载同步计数器（21），并为每第N个数据帧提供使能信号FE，其中N是大于零的整数并且是可选择的。选通布置（26）由使能信号FE控制，使得对于每第N帧数据刷新有源矩阵显示，从而允许显示器的功耗降低。

9. 发明授权

US06445323B1 Multi-format active matrix displays 有权
公开(公告)号：US06445323B1
公开(公告)日：2002-09-03
申请号：US09943593
申请日：2001-08-30
申请人： Graham Andrew Cairns , Michael James Brownlow
发明人： Graham Andrew Cairns , Michael James Brownlow
IPC分类号： H03M166
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/0248 , G09G2310/027 , G09G2320/0276 , G09G2330/021 , G09G2340/0428 , G09G2340/12 , G09G2340/125
摘要： Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

10. 发明授权

US06404230B1 Level-shifting pass gate 有权
标题翻译：电平转换通道
公开(公告)号：US06404230B1
公开(公告)日：2002-06-11
申请号：US09803125
申请日：2001-03-09
申请人： Graham Andrew Cairns , Michael James Brownlow
发明人： Graham Andrew Cairns , Michael James Brownlow
IPC分类号： H03K190175
CPC分类号： H03K19/018521 , H03K19/09429
摘要： A level-shifting pass gate comprises a field effect transistor (M1) whose source is connected to a signal input (IN) and whose drain is connected to a signal output (OUT). A load (R) is connected between the drain of the transistor (M1) and a supply line (vdd). A control means (1) has an enable input (EN) which receives signals for enabling or disabling the pass gate. When the gate is enabled, the control means (1) controls the transistor (M1) and possibly the load (R) so that an input logic low level is passed substantially unchanged whereas a relatively low input high level is shifted to a higher output logic high level approaching the supply voltage. When the pass gate is disabled, the transistor (M1) is switched off so that the input (IN) is isolated from the output (OUT) and assumes a high impedance state. Conversely, when disabled, the output (OUT) defaults to a predetermined state, such as logic low, logic high or high impedance.
摘要翻译：电平移动通过门包括其源极连接到信号输入（IN）并且其漏极连接到信号输出（OUT）的场效应晶体管（M1）。负载（R）连接在晶体管（M1）的漏极和电源线（vdd）之间。控制装置（1）具有使能输入（EN），其接收用于启用或禁用通过门的信号。当门被使能时，控制装置（1）控制晶体管（M1）和可能的负载（R），使得输入逻辑低电平基本上不变，而相对低的输入高电平被转移到较高的输出逻辑高电平接近电源电压。当禁止通电门时，晶体管（M1）关闭，使得输入（IN）与输出（OUT）隔离并呈现高阻抗状态。相反，当禁用时，输出（OUT）默认为预定状态，例如逻辑低电平，逻辑高电平或高阻抗。

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