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1. 发明授权

US06760333B1 Hybrid digital subscriber loop and voice-band universal serial bus modem 有权
标题翻译：混合数字用户环路和语音通用串行总线调制解调器
公开(公告)号：US06760333B1
公开(公告)日：2004-07-06
申请号：US09507314
申请日：2000-02-18
申请人： Michael J. Moody , Magnus G. Karlsson , Norayda N. Humphrey , Gregory Lee Christison
发明人： Michael J. Moody , Magnus G. Karlsson , Norayda N. Humphrey , Gregory Lee Christison
IPC分类号： H04L1228
CPC分类号： H04L12/44 , H04L12/403 , H04L2012/5606 , H04L2012/5616 , H04L2012/6427 , H04L2012/6478
摘要： A Universal Serial Bus (USB) modem (14) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) and contains a shared memory (44) in which USB endpoints are established for data communication. In the DSL mode, an ATM receive controller (134) receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine the virtual connection to the corresponding cell, and then forwards the payload portion of the ATM cell, but not the ATM cell header. In the voice-band mode, the ATM receive controller (134) and ATM transmit controller (132) operate in a simple streaming mode. A host interface controller (135) is also provided, by way of which facsimile communications are carried out simultaneously with DSL communications, or in separate sessions relative to voice-band data communications.
摘要翻译：公开了具有两种操作模式的通用串行总线（USB）调制解调器（14），即数字用户环路（DSL）模式和语音频带模式。 USB接口设备（30）耦合到数字信号处理器（DSP）（32）并且包含共享存储器（44），其中建立USB端点用于数据通信。在DSL模式中，ATM接收控制器（134）从DSP（32）接收每个ATM信元，并询问ATM信元报头以确定到相应小区的虚拟连接，然后转发ATM信元的有效载荷部分，但是不是ATM信元头。在语音频带模式中，ATM接收控制器（134）和ATM发送控制器（132）以简单的流模式操作。还提供主机接口控制器（135），通过该主机接口控制器（135）可以与DSL通信同时执行传真通信，或者相对于语音频带数据通信进行单独的会话。

2. 发明授权

US07215670B1 Hardware acceleration for reassembly of message packets in a universal serial bus peripheral device 有权
标题翻译：在通用串行总线外围设备中重新组装消息包的硬件加速
公开(公告)号：US07215670B1
公开(公告)日：2007-05-08
申请号：US09507249
申请日：2000-02-18
申请人： Magnus G. Karlsson , Norayda N. Humphrey , Gregory Lee Christison
发明人： Magnus G. Karlsson , Norayda N. Humphrey , Gregory Lee Christison
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/606 , H04L49/608 , H04L2012/5618 , H04L2012/5651 , H04L2012/5652 , H04L2012/5665 , H04L2012/5681
摘要： A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (51) are established, at which received ATM cell payload data may be stored. An ATM receive controller (134) is provided in the USB interface device (30), which receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine which, if any, virtual connection the cell corresponds. The ATM receive controller (134) then forwards the payload portion of the ATM cell, but not the ATM cell header, to the endpoint (51) corresponding to the virtual connection to which the ATM cell is directed. The disclosed ATM receive controller (134) also includes logic (64) for calculating a cyclic redundancy check value over the payload portion of the ATM cells that make up an ATM packet.
摘要翻译：公开了一种在主计算机（12）之外执行重组和分割操作的通用串行总线（USB）调制解调器（14）。 USB接口设备（30）耦合到调制解调器（14）中的数字信号处理器（DSP）（32），并且包含其中建立批量端点（51）的共享存储器（44），其中接收的ATM信元可以存储有效载荷数据。在USB接口设备（30）中提供ATM接收控制器（134），其从DSP（32）接收每个ATM信元，并询问ATM信元报头，以确定该信元对应的虚拟连接（如果有的话）。 ATM接收控制器（134）然后将ATM信元的有效载荷部分（而不是ATM信元报头）转发到对应于ATM信元所针对的虚拟连接的端点（51）。所公开的ATM接收控制器（134）还包括用于在构成ATM分组的ATM信元的有效载荷部分上计算循环冗余校验值的逻辑（64）。

3. 发明授权

US06804243B1 Hardware acceleration for segmentation of message packets in a universal serial bus peripheral device 有权
标题翻译：通用串行总线外围设备中消息分组的硬件加速
公开(公告)号：US06804243B1
公开(公告)日：2004-10-12
申请号：US09507383
申请日：2000-02-18
申请人： Norayda N. Humphrey , Magnus G Karlsson , Gregory Lee Christison
发明人： Norayda N. Humphrey , Magnus G Karlsson , Gregory Lee Christison
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L2012/5614 , H04L2012/5665
摘要： A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (240) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller (132) retrieves the header portion of the ATM packet from a transmit endpoint (240) and stores the information in registers (252, 254, 256) in the ATM transmit controller (132). A four-byte ATM cell header is then transmitted to byte buffers (268) and to the DSP (32) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint (240) in shared memory (44), and forwarded to byte buffers (268) for transmission.
摘要翻译：公开了一种在主计算机（12）之外执行重组和分割操作的通用串行总线（USB）调制解调器（14）。 USB接口设备（30）耦合到调制解调器（14）中的数字信号处理器（DSP）（32），并且包含其中建立批量端点（240）的共享存储器（44），在该数据信号处理器并且在传输之前存储有效载荷数据。 ATM发送控制器（132）从发送端点（240）检索ATM分组的报头部分，并将信息存储在ATM发送控制器（132）中的寄存器（252,254,256）中。然后将四字节的ATM信元报头发送到字节缓冲器（268）和DSP（32），以在通信设施上传输。之后，从共享存储器（44）中的发送端点（240）检索有效载荷数据，并转发到字节缓冲器（268）以进行传输。

4. 发明授权

US06523081B1 Architecture using dedicated endpoints and protocol for creating a multi-application interface and improving bandwidth over universal serial bus 有权
标题翻译：使用专用端点和协议创建多应用接口并通过通用串行总线改善带宽的架构
公开(公告)号：US06523081B1
公开(公告)日：2003-02-18
申请号：US09506764
申请日：2000-02-18
申请人： Magnus G. Karlsson , Michael J. Moody , Gregory Lee Christison
发明人： Magnus G. Karlsson , Michael J. Moody , Gregory Lee Christison
IPC分类号： G06F1338
CPC分类号： H04L12/4625
摘要： A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host, where the circuitry for providing a capability comprises an address space (VBUS). The USB function device (14) further comprises a USB interface circuit (30) coupled between the USB host and the circuitry for providing a capability to the USB host. The USB interface circuit (30) comprises a memory area (44, 106) comprising a write endpoint (1062) accessible to the USB host for writing a plurality of bytes to the memory area via the write endpoint. The plurality of bytes comprise data information and protocol information. The write endpoint comprises an endpoint-type other than a control-type endpoint. The USB interface circuit also comprises circuitry for decoding (166) the protocol information and circuitry for communicating the data information to the address space in response to the protocol information.
摘要翻译：一种用于耦合到USB主机（12）的USB功能设备（14）。 USB功能设备（14）包括用于向USB主机提供能力的电路（32），其中用于提供能力的电路包括地址空间（VBUS）。 USB功能设备（14）还包括耦合在USB主机和用于向USB主机提供能力的电路之间的USB接口电路（30）。 USB接口电路（30）包括一个存储器区域（44,106），该存储器区域包括可由USB主机访问的写入端点（1062），用于经由写入端点向存储器区域写入多个字节。多个字节包括数据信息和协议信息。写入端点包括除控制类型端点之外的端点类型。 USB接口电路还包括用于解码协议信息的电路（166）和用于响应协议信息将数据信息传送到地址空间的电路。

5. 发明授权

US06671765B1 Architecture enabling code overlay using a dedicated endpoint 有权
标题翻译：使用专用端点启用代码覆盖的架构
公开(公告)号：US06671765B1
公开(公告)日：2003-12-30
申请号：US09506613
申请日：2000-02-18
申请人： Magnus G. Karlsson , Gregory Lee Christison
发明人： Magnus G. Karlsson , Gregory Lee Christison
IPC分类号： G06F1336
CPC分类号： G06F9/445
摘要： A USB function device (14) for coupling to a USB host (12). The USB function device (14), comprises circuitry (32) for providing a capability to the USB host, where the circuitry for the capability comprises an address space. The USB function device further comprises a USB interface circuit (136) coupled between the USB host (12) and the circuitry (32) for providing a capability to the USB host. The USB interface circuit comprises a memory area (106) comprising a code overlay endpoint (1061) accessible to the USB host for writing two or more code blocks to the code overlay endpoint. The USB interface circuit further comprises circuitry (150-163) for communicating a first of the code blocks from the code overlay endpoint to the address space and for subsequently communicating a second of the code blocks from the code overlay endpoint to the address space. The circuitry for communicating is operable to communicate a code block from the code overlay endpoint to the address space after a start-up time of the USB function device.
摘要翻译：一种用于耦合到USB主机（12）的USB功能设备（14）。 USB功能设备（14）包括用于向USB主机提供能力的电路（32），其中用于该能力的电路包括地址空间。 USB功能设备还包括耦合在USB主机（12）和电路（32）之间的USB接口电路（136），用于向USB主机提供能力。 USB接口电路包括存储区域（106），该存储器区域（106）包括USB主机可访问的代码覆盖端点（1061），用于将两个或更多个代码块写入代码覆盖端点。 USB接口电路还包括用于将代码块中的第一代码块从代码覆盖端点传送到地址空间的电路（150-163），并且用于随后将代码块中的第二代码块从代码覆盖端点传送到地址空间。用于通信的电路可操作以在USB功能设备的启动时间之后将码块从代码覆盖端点传送到地址空间。

6. 发明授权

US08130889B2 Receive timing manager 有权
标题翻译：接收定时管理器
公开(公告)号：US08130889B2
公开(公告)日：2012-03-06
申请号：US11098130
申请日：2005-04-04
申请人： Denis Roland Beaudoin , Ritesh Dhirajlal Sojitra , Gregory Lee Christison
发明人： Denis Roland Beaudoin , Ritesh Dhirajlal Sojitra , Gregory Lee Christison
IPC分类号： H04L7/02
CPC分类号： H04L7/0338
摘要： A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
摘要翻译：介绍了一种新颖的接收时序管理器。本发明的优选实施例包括用于检测数据转换点的边缘检测逻辑，用于在不同采样点存储数据的多个数据触发器，以及多路复用器，用于基于找到的转换点来选择理想采样点。样品窗口由多个样品制成。基于数据传输速度和精度要求，样本窗口大小可以设计为比系统时钟周期更小或更大。

7. 发明授权

US07269175B2 AAL2 transmitter for voice-packed and signaling management-packed interleaving on an ATM connection 有权
标题翻译： AAL2发送器，用于ATM连接上的语音封装和信令管理封装交织
公开(公告)号：US07269175B2
公开(公告)日：2007-09-11
申请号：US09827816
申请日：2001-04-06
申请人： Magnus Karlsson , Gregory Lee Christison , Norayda Humphrey
发明人： Magnus Karlsson , Gregory Lee Christison , Norayda Humphrey
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5653 , H04L2012/5656 , H04L2012/5671 , H04Q2213/13034 , H04Q2213/13107 , H04Q2213/1329 , H04Q2213/13396
摘要： The present invention provides an apparatus, system and method for transmitting asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system (160) and a host processor (190). The transmitter interfaces directly with the DSP sub-system (160) (which converts the digitized voice samples into voice signals) and the host processor (190) (which performs AAL2 signaling and layer management functions). The transmitter is configured to interleave AAL2 voice packets from the DSP sub-system (160) and signaling and management packets from the host processor (190) on an ATM connection. Data is fetched by DMA(s) (415). A channel look-up table uses the DSP assigned voice channel as an index into the table to map a voice channel to the ATM connection.
摘要翻译：本发明提供了一种用于在ATM系统中的ATM适配层（AAL）配置的连接上发送异步传输模式（ATM）数据信元的装置，系统和方法，该ATM系统包括数字信号处理器（DSP）子系统（160）和主机处理器（190）。发射机直接与DSP子系统（160）（其将数字化语音样本转换成语音信号）和主处理器（190）（其执行AAL2信令和层管理功能）直接接口。发射机被配置为在ATM连接上交织来自DSP子系统（160）的AAL2语音分组和来自主处理器（190）的信令和管理分组。数据由DMA（415）取出。信道查找表使用DSP分配的语音信道作为表中的索引，以将语音信道映射到ATM连接。

8. 发明授权

US06990108B2 ATM system architecture for the convergence of data, voice and video 有权
标题翻译： ATM系统架构用于数据，语音和视频的融合
公开(公告)号：US06990108B2
公开(公告)日：2006-01-24
申请号：US09827829
申请日：2001-04-06
申请人： Magnus Karlsson , Gregory Lee Christison , Norayda Humphrey
发明人： Magnus Karlsson , Gregory Lee Christison , Norayda Humphrey
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5618 , H04L2012/5651 , H04L2012/5656 , H04L2012/5658
摘要： The present invention provides a unitary mechanism for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM module (101) for convergence of the telecommunications traffic includes an ATM processor (120) configured to perform QoS, OAM processing and switching in an ATM system. Function modules (102,104,105) and data ports (106,108) are configurable to transceive data, voice and video traffic in which the traffic is packetized in ATM data cells.
摘要翻译：本发明提供了一种使用异步传输模式（ATM）架构的高速端到端电信业务的统一机制，用于在使用DSL路由器的SOHO应用中的视频，数据和语音的收敛。用于电信业务的收敛的ATM模块（101）包括被配置为在ATM系统中执行QoS，OAM处理和切换的ATM处理器（120）。功能模块（102,104,105）和数据端口（106,108）可配置为收发数据，语音和视频流量，其中流量在ATM数据单元中分组化。

9. 发明授权

US08983012B2 Receive timing manager 有权
标题翻译：接收定时管理器
公开(公告)号：US08983012B2
公开(公告)日：2015-03-17
申请号：US13358183
申请日：2012-01-25
申请人： Denis Roland Beaudoin , Ritesh Dhirajlal Sojitra , Gregory Lee Christison
发明人： Denis Roland Beaudoin , Ritesh Dhirajlal Sojitra , Gregory Lee Christison
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0338
摘要： A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
摘要翻译：介绍了一种新颖的接收时序管理器。本发明的优选实施例包括用于检测数据转换点的边缘检测逻辑，用于在不同采样点存储数据的多个数据触发器，以及多路复用器，用于基于找到的转换点来选择理想采样点。样品窗口由多个样品制成。基于数据传输速度和精度要求，样本窗口大小可以设计为比系统时钟周期更小或更大。

10. 发明申请

US20120121051A1 RECEIVE TIMING MANAGER 有权
标题翻译：接收时间管理员
公开(公告)号：US20120121051A1
公开(公告)日：2012-05-17
申请号：US13358183
申请日：2012-01-25
申请人： Denis Roland Beaudoin , Ritesh Dhirajlal Sojitra , Gregory Lee Christison
发明人： Denis Roland Beaudoin , Ritesh Dhirajlal Sojitra , Gregory Lee Christison
IPC分类号： H04L7/033 , H03L7/00
CPC分类号： H04L7/0338
摘要： A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
摘要翻译：介绍了一种新颖的接收时序管理器。本发明的优选实施例包括用于检测数据转换点的边缘检测逻辑，用于在不同采样点存储数据的多个数据触发器，以及多路复用器，用于基于找到的转换点来选择理想采样点。样品窗口用多个样品制成。基于数据传输速度和精度要求，样本窗口大小可以设计为比系统时钟周期更小或更大。

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