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1. 发明授权

US5938739A Memory controller including write posting queues, bus read control logic, and a data contents counter 失效
标题翻译：存储器控制器包括写入寄存队列，总线读取控制逻辑和数据内容计数器
公开(公告)号：US5938739A
公开(公告)日：1999-08-17
申请号：US811587
申请日：1997-03-05
申请人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
发明人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00 , G06F13/14
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。

2. 发明授权

US5634073A System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation 失效
标题翻译：具有与不同类型的写入操作相关联的多个发布队列的系统，用于基于读取操作的类型选择性地检查一个队列
公开(公告)号：US5634073A
公开(公告)日：1997-05-27
申请号：US324246
申请日：1994-10-14
申请人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
发明人： Michael J. Collins , Gary W. Thome , Michael P. Moriarty , Jens K. Ramsey , John E. Larson
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0831 , G06F13/1605 , G06F13/1642 , G06F13/1694
摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.
摘要翻译：存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。内容可寻址存储器（CAM）被用作PCI到存储器队列。当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

3. 发明授权

US06209067B1 Computer system controller and method with processor write posting hold off on PCI master memory request 失效
标题翻译：具有处理器写入寄存功能的计算机系统控制器和方法在PCI主存储器请求中保持不变
公开(公告)号：US06209067B1
公开(公告)日：2001-03-27
申请号：US08566514
申请日：1995-12-04
申请人： Michael J. Collins , Michael P. Moriarty , John E. Larson , Jens K. Ramsey
发明人： Michael J. Collins , Michael P. Moriarty , John E. Larson , Jens K. Ramsey
IPC分类号： G06F1336
CPC分类号： G06F13/1605 , G06F12/0831 , G06F13/1642 , G06F13/1694
摘要： A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.
摘要翻译：包括存储器控制器的计算机系统在处理器与外围部件互连（PCI）总线和存储器系统之间提供一系列的队列。内存一致性以两种不同的方式保持。在PCI总线接受任何读操作之前，两个发送队列都必须为空。在PCI设备可以访问内存之前，必须刷新处理器到PCI写入的写入队列。如果PCI设备请求存储器读取队列不为空，则在刷新写入过帐队列时，强制PCI设备重试该操作。此外，当刷新队列时，防止处理器进一步发布到队列。定时器提供进一步的临时时间，使处理器不被发布以允许足够的时间使PCI主机重试该操作。

4. 发明授权

US5781925A Method of preventing cache corruption during microprocessor pipelined burst operations 失效
标题翻译：在微处理器流水线突发操作期间防止高速缓存损坏的方法
公开(公告)号：US5781925A
公开(公告)日：1998-07-14
申请号：US567030
申请日：1995-12-04
申请人： John E. Larson , Jens K. Ramsey , Jeffrey C. Stevens , Michael J. Collins
发明人： John E. Larson , Jens K. Ramsey , Jeffrey C. Stevens , Michael J. Collins
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0879 , G06F12/0859
摘要： In a microcomputer system implementing cache memory, the microprocessor can execute back-to-back pipelined burst operations without corrupting the internal address of the cache memory. The address strobe from the processor is blocked by the cache memory controller, allowing a burst operation to complete from or to the cache memories before the second address is strobed into the cache.
摘要翻译：在实现高速缓冲存储器的微计算机系统中，微处理器可以执行背靠背流水线突发操作，而不会破坏高速缓冲存储器的内部地址。来自处理器的地址选通脉冲被高速缓存存储器控制器阻挡，允许突发操作在第二地址被选通到高速缓存之前从高速缓存存储器完成。

5. 发明授权

US5640532A Microprocessor cache memory way prediction based on the way of previous memory read 失效
标题翻译：基于先前存储器读取方式的微处理器缓存存储器方式预测
公开(公告)号：US5640532A
公开(公告)日：1997-06-17
申请号：US323432
申请日：1994-10-14
申请人： Gary W. Thome , Jens K. Ramsey
发明人： Gary W. Thome , Jens K. Ramsey
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： In a microcomputer system using a multiple-way cache memory subsystem, the way of the next microprocessor operation is predicted, and either the output enables of the cache are predriven, or, in a single-bank multiple-way cache, the address bit which acts as a way selection is appropriately set. The way prediction used is based not on the address being accessed in the cache, but instead on the last processor code read, or the last processor code or data read. This permits the cache memory subsystem to respond more quickly on hits to the appropriate way, and also allows for slower cache memories to be used without reducing performance.
摘要翻译：在使用多路缓存存储器子系统的微计算机系统中，预测下一个微处理器操作的方式，并且高速缓存的输出使能被预先驱动，或者在单行多路缓存中，地址位作为方式选择的适当设定。所使用的预测方式不是基于缓存中访问的地址，而是基于最后一个处理器代码读取，或最后一个处理器代码或数据读取。这允许高速缓存存储器子系统以适当的方式更快地响应命中，并且还允许使用较慢的高速缓冲存储器而不降低性能。

6. 发明授权

US5822756A Microprocessor cache memory way prediction based on the way of a previous memory read 失效
标题翻译：基于先前存储器读取方式的微处理器缓存存储器方式预测
公开(公告)号：US5822756A
公开(公告)日：1998-10-13
申请号：US839158
申请日：1997-04-23
申请人： Gary W. Thome , Jens K. Ramsey
发明人： Gary W. Thome , Jens K. Ramsey
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： In a microcomputer system using a multiple-way cache memory subsystem, the way of the next microprocessor operation is predicted, and either the output enables of the cache are predriven, or, in a single-bank multiple-way cache, the address bit which acts as a way selection is appropriately set. The way prediction used is based not on the address being accessed in the cache, but instead on the last processor code read, or the last processor code or data read. This permits the cache memory subsystem to respond more quickly on hits to the appropriate way, and also allows for slower cache memories to be used without reducing performance.
摘要翻译：在使用多路缓存存储器子系统的微计算机系统中，预测下一个微处理器操作的方式，并且高速缓存的输出使能被预先驱动，或者在单行多路缓存中，地址位作为方式选择的适当设定。所使用的预测方式不是基于缓存中访问的地址，而是基于最后一个处理器代码读取，或最后一个处理器代码或数据读取。这允许高速缓存存储器子系统以适当的方式更快地响应命中，并且还允许使用较慢的高速缓冲存储器而不降低性能。

7. 发明授权

US07120758B2 Technique for improving processor performance 失效
标题翻译：提高处理器性能的技术
公开(公告)号：US07120758B2
公开(公告)日：2006-10-10
申请号：US10365018
申请日：2003-02-12
申请人： Phillip M. Jones , Robert A. Lester , Jens K. Ramsey , William J. Walker , John E. Larson , James Andre , Paul Rawlins
发明人： Phillip M. Jones , Robert A. Lester , Jens K. Ramsey , William J. Walker , John E. Larson , James Andre , Paul Rawlins
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G06F13/1673
摘要： Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.
摘要翻译：提高处理器性能的方法和装置。在一些实施例中，可以通过在初始请求期间通过后续请求重用存储在缓冲器中的数据来改善处理速度。控制器中的临时存储缓冲区的分配可以做出以允许数据重用的潜力。此外，可以指定热缓冲器以允许重新使用存储在热缓冲器中的数据。在随后的请求中，存储在热缓冲器中的数据可以被发送到请求设备而不从存储器重新检索数据。

8. 发明授权

US5835948A Single bank, multiple way cache memory 失效
标题翻译：单行，多路缓存存储器
公开(公告)号：US5835948A
公开(公告)日：1998-11-10
申请号：US324016
申请日：1994-10-14
申请人： Sompong P. Olarig , Jens K. Ramsey , Michael J. Collins
发明人： Sompong P. Olarig , Jens K. Ramsey , Michael J. Collins
IPC分类号： G06F12/08
CPC分类号： G06F12/0879 , G06F12/0859
摘要： In a microcomputer system implementing cache memory, a multiple-way cache is implemented in a single-bank memory. Instead of using chip output enables on a separate physical chip for each way of the multiple-way cache, an address line of a single bank of memory is used to select between ways. In this way, fewer parts can be used, and a single-bank memory can be used for a multiple-way cache.
摘要翻译：在实现高速缓冲存储器的微计算机系统中，在单行存储器中实现多路高速缓存。代替使用芯片输出，可以在多路缓存的每种方式的单独物理芯片上实现，单个存储器的地址线用于在各种方式之间进行选择。以这种方式，可以使用更少的部件，并且单行存储器可以用于多路缓存。

9. 发明授权

US5699550A Computer system cache performance on write allocation cycles by immediately setting the modified bit true 失效
标题翻译：计算机系统缓存性能在写入分配周期时立即将修改的位设置为true
公开(公告)号：US5699550A
公开(公告)日：1997-12-16
申请号：US323260
申请日：1994-10-14
申请人： Jens K. Ramsey
发明人： Jens K. Ramsey
IPC分类号： G06F12/08
CPC分类号： G06F12/0802
摘要： In a microcomputer system implementing a cache memory subsystem, the cache performance on write allocation cycles is improved. When the processor writes to a line of the cache memory that results in a cache tag miss, after the processor write operation is suspended, the data is allocated from main memory into the cache memory. During this main memory read, however, instead of setting the state of the line of memory to unmodified, its state is set to modified. On the subsequent processor read operation, a cycle is saved because the modified bit does not have to be changed from unmodified to modified.
摘要翻译：在实现高速缓存存储器子系统的微计算机系统中，提高了写入分配周期的高速缓存性能。当处理器写入高速缓存存储器的一行导致高速缓存标签未命中时，在处理器写入操作被暂停之后，数据从主存储器分配到高速缓冲存储器中。然而，在该主存储器读取期间，不是将存储器行的状态设置为未修改，而是将其状态设置为修改。在随后的处理器读取操作中，保存一个周期，因为修改的位不必从未修改更改为修改。

10. 发明授权

US5426765A Multiprocessor cache abitration 失效
标题翻译：多处理器缓存引导
公开(公告)号：US5426765A
公开(公告)日：1995-06-20
申请号：US227303
申请日：1994-04-13
申请人： Jeffrey C. Stevens , Mike T. Jackson , Roger E. Tipley , Jens K. Ramsey , Sompong Olarig , Philip C. Kelly
发明人： Jeffrey C. Stevens , Mike T. Jackson , Roger E. Tipley , Jens K. Ramsey , Sompong Olarig , Philip C. Kelly
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00
CPC分类号： G06F12/0831 , G06F13/18
摘要： A method for arbitrating between processor and host bus snoop accesses to a cache subsystem in a multiprocessor system where the processor does not allow for processor cycle aborts. When a processor access and a snoop access both occur and no tag access or tag modify cycle is currently being performed, the snoop access is given priority over the processor access. After an initial arbitration, if any, the processor and snoop accesses alternate tag access if both processor and snoop accesses are active. This balances any wait states incurred between the processor and the host bus and ensures that neither bus is locked out by continual accesses by the other. In addition, tag modify cycles are generally run immediately after the tag access cycles that initiate them.
摘要翻译：一种用于在处理器不允许处理器周期中止的多处理器系统中的处理器和主机总线窥探访问缓存子系统之间进行仲裁的方法。当处理器访问和窥探访问都发生，并且当前没有执行标签访问或标签修改周期时，侦听访问被优先于处理器访问。在初始仲裁（如果有的话）之后，如果处理器和侦听访问都处于活动状态，则处理器和侦听器访问备用标签访问。这将平衡处理器和主机总线之间发生的任何等待状态，并确保总线不被另一个的连续访问锁定。此外，标签修改周期通常在启动它们的标签访问周期之后立即运行。

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