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    • 6. 发明申请
    • System, method and operating unit for forming mixed layers for pallets
    • 用于形成托盘混合层的系统,方法和操作单元
    • US20100228385A1
    • 2010-09-09
    • US12660727
    • 2010-03-03
    • Michael BeckMarkus Ludsteck
    • Michael BeckMarkus Ludsteck
    • G06F7/00B65G57/00G06F3/048
    • B65G1/1378B65G47/086B65G57/24B65G60/00B65G61/00
    • A system (1), a method and an operating unit (62) for the creation of mixed layers for pallets (81, 82, 83, 84) are disclosed. A storage (10) is provided in which at least two different pack types are stored on a plurality of pallets (81, 82, 83, 84), including a plurality of layers of homogenous packs. The packs are intermediately stored in a plurality of individual, parallel conveyors (301, 302, . . . 30N) in a homogenous state. Based on the input of a user (5) on a touch panel (62), the packs are supplied to a grouping table (50) via a supply conveyor (40) in a predetermined sequence. A controller (60) is associated with the system (1) so that, in the grouping table (50), individual different pack types are allocated to the predefined positions of the different pack types as a function of predefined positions of the different pack types in a layer pattern (14) of a layer (24) of a production pallet (12).
    • 公开了一种用于产生用于托盘(81,82,83,84)的混合层的方法和操作单元(62)。 提供了一种存储装置,其中至少两种不同的包装类型存储在多个包括多层均匀包装的托盘(81,82,83,84)中。 这些包装以均匀的状态中间存储在多个单独的平行输送机(301,302,...,30N)中。 基于触摸面板(62)上的用户(5)的输入,经由供给传送器(40)以预定的顺序将包提供给分组表(50)。 控制器(60)与系统(1)相关联,使得在分组表(50)中,根据不同包装类型的预定位置的函数将单独的不同包类型分配给不同包类型的预定义位置 在生产托盘(12)的层(24)的层图案(14)中。
    • 8. 发明授权
    • Metal interconnect structure and method
    • 金属互连结构和方法
    • US07651942B2
    • 2010-01-26
    • US11203883
    • 2005-08-15
    • Frank HuebingerMichael Beck
    • Frank HuebingerMichael Beck
    • H01L21/4763
    • H01L21/76808H01L21/02063H01L21/76805H01L21/76814
    • A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.
    • 一种制造半导体器件的方法,该半导体器件包括具有形成在第一介电层中的导电区域的金属互连结构和上覆的低k电介质层。 在上覆电介质层中的双镶嵌结构中形成通孔和沟槽,通孔与导电区域和沟槽对准。 用于释放有机残余物的牺牲衬垫沉积在晶片的通孔和上表面上,沉积有机平坦化层。 用干等离子体蚀刻除去有机平坦化层,然后进行湿法清洁以除去牺牲衬垫。 将导电材料与电介质层分离的扩散阻挡层沉积在双镶嵌结构上并在晶片的上表面上。 导电结构形成在扩散阻挡层上并被抛光以形成用于进一步处理步骤的均匀表面。