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1. 发明授权

US08331134B2 Non-volatile static random access memory and operation method thereof 有权
标题翻译：非易失性静态随机存取存储器及其操作方法
公开(公告)号：US08331134B2
公开(公告)日：2012-12-11
申请号：US12853301
申请日：2010-08-10
申请人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
发明人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C14/0054 , G11C14/009
摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.
摘要翻译：提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二开关的第二端子分别连接到第一和第二位线。第一和第二开关的控制端子连接到字线。第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二NVM的第二端子分别连接到第一和第二位线。第一和第二NVM的使能端子连接到使能线。

2. 发明授权

US08213213B2 Reference current generator for resistance type memory and method thereof 有权
标题翻译：电阻型存储器的参考电流发生器及其方法
公开(公告)号：US08213213B2
公开(公告)日：2012-07-03
申请号：US12614631
申请日：2009-11-09
申请人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
发明人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C5/147 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C2013/0054
摘要： A reference current generator for a resistance type memory and a method thereof is disclosed. The reference current generator comprises N parallel circuit sets. Each of the N parallel circuit sets is formed with at least one first reference element and second reference elements connected in parallel. The number of the first reference elements plus the number of the second reference elements is N. The resistance value of first reference elements (a first resistance value) is not equal to the resistance value of the second reference elements (a second resistance value). An equivalent resistance provided with a equivalent resistance value between the first and second resistance value is formed by connecting the N parallel circuit sets in series between an input terminal and output terminal. A reference current is outputted from the output terminal by applying an operation voltage to the input terminal.
摘要翻译：公开了一种用于电阻型存储器的参考电流发生器及其方法。参考电流发生器包括N个并联电路组。 N个并联电路组中的每一个形成有并联连接的至少一个第一参考元件和第二参考元件。第一参考元件的数量加上第二参考元件的数量为N.第一参考元件（第一电阻值）的电阻值不等于第二参考元件的电阻值（第二电阻值）。通过在输入端子和输出端子之间串联连接N个并联电路组来形成具有第一和第二电阻值之间的等效电阻值的等效电阻。通过对输入端施加工作电压，从输出端子输出基准电流。

3. 发明申请

US20110280073A1 NON-VOLATILE STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF 有权
标题翻译：非易失性静态随机访问存储器及其操作方法
公开(公告)号：US20110280073A1
公开(公告)日：2011-11-17
申请号：US12853301
申请日：2010-08-10
申请人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
发明人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
IPC分类号： G11C14/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C14/0054 , G11C14/009
摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.
摘要翻译：提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二开关的第二端子分别连接到第一和第二位线。第一和第二开关的控制端子连接到字线。第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二NVM的第二端子分别连接到第一和第二位线。第一和第二NVM的使能端子连接到使能线。

4. 发明申请

US20110110140A1 REFERENCE CURRENT GENERATOR FOR RESISTANCE TYPE MEMORY AND METHOD THEREOF 有权
标题翻译：用于电阻型存储器的参考电流发生器及其方法
公开(公告)号：US20110110140A1
公开(公告)日：2011-05-12
申请号：US12614631
申请日：2009-11-09
申请人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
发明人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
IPC分类号： G11C11/00 , G11C7/02 , G11C5/14
CPC分类号： G11C7/14 , G11C5/147 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C2013/0054
摘要： A reference current generator for a resistance type memory and a method thereof is disclosed. The reference current generator comprises N parallel circuit sets. Each of the N parallel circuit sets is formed with at least one first reference element and second reference elements connected in parallel. The number of the first reference elements plus the number of the second reference elements is N. The resistance value of first reference elements (a first resistance value) is not equal to the resistance value of the second reference elements (a second resistance value). An equivalent resistance provided with a equivalent resistance value between the first and second resistance value is formed by connecting the N parallel circuit sets in series between an input terminal and output terminal. A reference current is outputted from the output terminal by applying an operation voltage to the input terminal.
摘要翻译：公开了一种用于电阻型存储器的参考电流发生器及其方法。参考电流发生器包括N个并联电路组。 N个并联电路组中的每一个形成有并联连接的至少一个第一参考元件和第二参考元件。第一参考元件的数量加上第二参考元件的数量为N.第一参考元件（第一电阻值）的电阻值不等于第二参考元件的电阻值（第二电阻值）。通过在输入端子和输出端子之间串联连接N个并联电路组来形成具有第一和第二电阻值之间的等效电阻值的等效电阻。通过对输入端施加工作电压，从输出端子输出基准电流。

5. 发明申请

US20130114325A1 NON-VOLATILE RANDOM ACCESS MEMORY COUPLED TO A FIRST, SECOND AND THIRD VOLTAGE AND OPERATION METHOD THEREOF 有权
标题翻译：非易失性随机访问存储器与第一，第二和第三电压和操作方法相关联
公开(公告)号：US20130114325A1
公开(公告)日：2013-05-09
申请号：US13332402
申请日：2011-12-21
申请人： Chih-He Lin , Wen-Pin Lin , Pi-Feng Chiu , Shyh-Shyuan Sheu
发明人： Chih-He Lin , Wen-Pin Lin , Pi-Feng Chiu , Shyh-Shyuan Sheu
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C14/009
摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.
摘要翻译：提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。开关的第二端子耦合到第三电压。

6. 发明申请

US20120320658A1 NONVOLATILE STATIC RANDOM ACCESS MEMORY CELL AND MEMORY CIRCUIT 有权
标题翻译：非易失性静态随机访问存储器单元和存储器电路
公开(公告)号：US20120320658A1
公开(公告)日：2012-12-20
申请号：US13230865
申请日：2011-09-13
申请人： Min-Chuan Wang , Pi-Feng Chiu , Shyh-Shyuan Sheu
发明人： Min-Chuan Wang , Pi-Feng Chiu , Shyh-Shyuan Sheu
IPC分类号： G11C11/00
CPC分类号： G11C14/0054
摘要： A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.
摘要翻译：提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由开关线路的开关信号控制，以将第一存储装置和第二存储装置导向同一位线或相同的补充位线。

7. 发明授权

US09086455B2 Testing and repairing apparatus of through silicon via in stacked-chip 有权
标题翻译：通过硅片通过堆芯片测试和修复设备
公开(公告)号：US09086455B2
公开(公告)日：2015-07-21
申请号：US13326331
申请日：2011-12-15
申请人： Hsin-Chi Lai , Chih-Sheng Lin , Pi-Feng Chiu , Zhe-Hui Lin
发明人： Hsin-Chi Lai , Chih-Sheng Lin , Pi-Feng Chiu , Zhe-Hui Lin
IPC分类号： G01R31/02 , G01R31/3185 , G01R31/28 , G01R31/317 , H01L21/66
CPC分类号： G01R31/318513 , G01R31/2812 , G01R31/31717 , H01L22/22
摘要： A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.
摘要翻译：提供了设置在第一和第二芯片之间的通过硅通孔（TSV）的测试和修复设备。第一和第二开关的第一端子耦合到TSV的第一端子。第三和第四开关的第一端子耦合到TSV的第二端子。第一电阻器的第一端子耦合到第一电压。第一选择器耦合在第二开关的第二端子和第一电阻器之间。第二选择器耦合在第四开关的第二端和第二电压之间。第一控制电路检测第二开关的第二端子，并控制第一开关，第二开关和第一选择器。第二控制电路控制第三开关，第四开关和第二选择器。

8. 发明授权

US08625361B2 Circuit and method for controlling write timing of a non-volatile memory 有权
标题翻译：用于控制非易失性存储器的写入定时的电路和方法
公开(公告)号：US08625361B2
公开(公告)日：2014-01-07
申请号：US13345740
申请日：2012-01-08
申请人： Pi-Feng Chiu , Shyh-Shyuan Sheu , Wen-Pin Lin , Chih-He Lin
发明人： Pi-Feng Chiu , Shyh-Shyuan Sheu , Wen-Pin Lin , Chih-He Lin
IPC分类号： G11C7/10 , G11C8/16
CPC分类号： G11C8/16 , G11C7/14 , G11C8/08 , G11C8/18 , G11C11/1675 , G11C11/1693 , G11C13/0004 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0078
摘要： A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.
摘要翻译：提供了用于控制非易失性存储器的写入定时的电路和方法。该方法包括以下步骤。首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。存储单元存储具有不同电阻状态的数据状态。通过定时控制线将写时序输入到存储单元。接下来，基于时钟信号和控制信号来生成写入定时。写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

9. 发明授权

US08422295B1 Non-volatile random access memory coupled to a first, second and third voltage and operation method thereof 有权
标题翻译：耦合到第一，第二和第三电压的非易失性随机存取存储器及其操作方法
公开(公告)号：US08422295B1
公开(公告)日：2013-04-16
申请号：US13332402
申请日：2011-12-21
申请人： Chih-He Lin , Wen-Pin Lin , Pi-Feng Chiu , Shyh-Shyuan Sheu
发明人： Chih-He Lin , Wen-Pin Lin , Pi-Feng Chiu , Shyh-Shyuan Sheu
IPC分类号： G11C14/00
CPC分类号： G11C14/009
摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.
摘要翻译：提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。开关的第二端子耦合到第三电压。

10. 发明授权

US08508983B2 Nonvolatile static random access memory cell and memory circuit 有权
标题翻译：非易失性静态随机存取存储单元和存储电路
公开(公告)号：US08508983B2
公开(公告)日：2013-08-13
申请号：US13230865
申请日：2011-09-13
申请人： Min-Chuan Wang , Pi-Feng Chiu , Shyh-Shyuan Sheu
发明人： Min-Chuan Wang , Pi-Feng Chiu , Shyh-Shyuan Sheu
IPC分类号： G11C11/00
CPC分类号： G11C14/0054
摘要： A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.
摘要翻译：提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由切换线的切换信号控制，以将第一存储装置和第二存储装置导入相同的位线或相同的补充位线。

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