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1. 发明专利

JP2012134514A SiGe DEVICE INCLUDING SiGe-EMBEDDED DUMMY PATTERN FOR REDUCING MICRO LOADING EFFECT 有权
标题翻译： SiGe器件包括用于减少微载物效应的SiGe嵌入式DUMMY模式
公开(公告)号：JP2012134514A
公开(公告)日：2012-07-12
申请号：JP2012022232
申请日：2012-02-03
申请人： Mediatek Inc , 聯發科技股▲ふん▼有限公司Mediatek Inc.
发明人： LEE TUNG-HSING , YANG MING-TZONG , CHENG TAO , KO CHING-CHUNG , CHANG TIEN-CHANG , CHANG YU-TUNG
IPC分类号： H01L27/088 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： PROBLEM TO BE SOLVED: To provide an improved SiGe device including an SiGe-embedded dummy pattern which surrounds the SiGe device and is specially designed so as to reduce micro loading effect during epitaxial growth of SiGe.SOLUTION: A semiconductor device including a dummy pattern for reducing micro loading effect includes: a semiconductor substrate 1 on which a middle annular region 300 is provided between an internal region 200 and an external region 400; an SiGe device 100 provided in the internal region 200 on the substrate; and a plurality of dummy patterns 20 provided in the middle annular region 300 on the substrate. At least one of the plurality of the dummy patterns 20 contains SiGe.
摘要翻译：解决的问题：提供一种改进的SiGe器件，其包括围绕SiGe器件的SiGe-嵌入的虚设图案，并被专门设计以便在SiGe的外延生长期间减小微负载效应。解决方案：包括用于减小微负载效应的虚拟图案的半导体器件包括：在内部区域200和外部区域400之间设置有中间环形区域300的半导体衬底1; 设置在基板上的内部区域200中的SiGe器件100; 以及设置在基板上的中间环形区域300中的多个虚设图案20。多个虚设图案20中的至少一个包含SiGe。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2009164548A SiGe DEVICE WITH SiGe-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT 有权
标题翻译：具有SiGe嵌入式DUMMY图案的SiGe器件用于缓解微载荷效应
公开(公告)号：JP2009164548A
公开(公告)日：2009-07-23
申请号：JP2008099955
申请日：2008-04-08
申请人： Mediatek Inc , 聯發科技股▲ふん▼有限公司
发明人： LEE TUNG-HSING , YANG MING-TZONG , CHENG TAO , KO CHING-CHUNG , CHANG TIEN-CHANG , CHANG YU-TUNG
IPC分类号： H01L29/78 , H01L21/20 , H01L29/786
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02658 , H01L21/823412 , H01L21/823418 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： PROBLEM TO BE SOLVED: To provide a configuration of an SiGe-embedded dummy pattern capable of alleviating a micro-loading effect.
SOLUTION: A semiconductor device with dummy patterns 20 for alleviating the micro-loading effect includes a semiconductor substrate 1 having thereon a middle annular region 300 between an inner region 200 and an outer region 400; the SiGe device 100 provided on the substrate within the inner region; and a plurality of dummy patterns provided on the substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够减轻微负载效应的嵌入SiGe的虚拟图案的构造。解决方案：具有用于减轻微负载效应的虚设图案20的半导体器件包括其内部区域200和外部区域400之间具有中间环形区域300的半导体衬底1; 设置在内部区域中的衬底上的SiGe器件100; 以及设置在中间环形区域内的基板上的多个虚设图案。至少一个虚拟图案包含SiGe。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009290191A Seal ring structure of integrated circuit 有权
标题翻译：集成电路密封圈结构
公开(公告)号：JP2009290191A
公开(公告)日：2009-12-10
申请号：JP2009000783
申请日：2009-01-06
申请人： Mediatek Inc , 聯發科技股▲ふん▼有限公司
发明人： LEE TUNG-HSING , CHANG TIEN-CHANG , CHUNG YUAN-HUNG
IPC分类号： H01L21/822 , H01L21/3205 , H01L23/52 , H01L27/04
CPC分类号： H01L23/5225 , H01L23/552 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an improved seal ring of an IC chip which reduces digital noise coupling caused by a digital circuit.
SOLUTION: A seal ring structure is provided along the periphery of an integrated circuit. The seal ring is divided into at least a first part 124a and a second part 124b. The second part is provided opposite to an analog and/or RF (radio frequency) circuit block so that the analog and/or RF (radio frequency) circuit block is shielded from noise. A deep N-type well 310 is provided in a P-type substrate 100 under the second part. The deep N-type well reduces noise coupling of the substrate.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少由数字电路引起的数字噪声耦合的IC芯片的改进的密封环。解决方案：沿着集成电路的外围提供密封环结构。密封圈分为至少第一部分124a和第二部分124b。第二部分与模拟和/或射频（射频）电路块相反地设置，使得模拟和/或RF（射频）电路块被屏蔽以免被噪声干扰。在第二部分的P型基板100内设置深N型孔310。深N型阱降低了衬底的噪声耦合。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009290197A Seal ring structure of integrated circuit 有权
标题翻译：集成电路密封圈结构
公开(公告)号：JP2009290197A
公开(公告)日：2009-12-10
申请号：JP2009064272
申请日：2009-03-17
申请人： Mediatek Inc , 聯發科技股▲ふん▼有限公司
发明人： LEE TUNG-HSING , CHANG TIEN-CHANG , CHUNG YUAN-HUNG
IPC分类号： H01L21/822 , H01L21/3205 , H01L23/52 , H01L27/04
CPC分类号： H01L23/5225 , H01L23/552 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an improved seal ring structure of an IC (integrated circuit) chip which reduces digital noise coupling caused by a digital circuit.
SOLUTION: A seal ring structure for an IC is provided along the periphery of the IC and includes a seal ring which is divided into at least a first part, and a second part provided opposite to an analog and/or RF (radio frequency) circuit block so that the analog and/or RF circuit block is shielded from noise, a P+ region located under the second part and provided in a P type substrate, and an STI (shallow trench isolation) structure surrounding the P+ region and extending in the lateral direction under the conductive wall at the second part.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供减少由数字电路引起的数字噪声耦合的IC（集成电路）芯片的改进的密封环结构。解决方案：IC的密封环结构沿着IC的周边设置，并且包括至少分成第一部分的密封环和与模拟和/或RF（无线电）相对设置的第二部分频率）电路块，使得模拟和/或RF电路块被屏蔽掉，位于第二部分下方并设置在P型衬底中的P +区域和围绕P +区域并延伸的STI（浅沟槽隔离）结构在第二部分的导电壁下方的横向方向上。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009206467A Dual cesl process 审中-公开
标题翻译：双CESL过程
公开(公告)号：JP2009206467A
公开(公告)日：2009-09-10
申请号：JP2008106217
申请日：2008-04-15
申请人： Mediatek Inc , 聯發科技股▲ふん▼有限公司
发明人： LEE TUNG-HSING , YANG MING-TZONG , KO CHING-CHUNG , CHANG TIEN-CHANG , CHANG YU-TUNG
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： PROBLEM TO BE SOLVED: To provide a dual CESL process capable of raising the performance of a semiconductor device. SOLUTION: A dual CESL process includes: (1) providing a substrate having thereon a first device region, a second device region and a shallow trench isolation (STI) region between the first and second device regions; (2) forming a first-stress imparting film with a first stress over the substrate, wherein the first-stress imparting film does not cover the second device region; and (3) forming a second-stress imparting film with a second stress over the substrate, wherein the second-stress imparting film does not cover the first device region, an overlapped boundary between the first- and second-stress imparting films is created directly above the STI region, and wherein the overlapped boundary is placed in close proximity to the second device region in order to induce the first stress to a channel region thereof in a transversal direction. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高半导体器件的性能的双CESL工艺。双重CESL方法包括：（1）提供其上具有第一和第二器件区域之间的第一器件区域，第二器件区域和浅沟槽隔离（STI）区域的衬底; （2）在所述基板上形成具有第一应力的第一应力赋予膜，其中所述第一应力赋予膜不覆盖所述第二器件区域; 和（3）在基板上形成具有第二应力的第二应力赋予膜，其中第二应力赋予膜不覆盖第一器件区域，直接产生第一和第二施加应力膜之间的重叠边界在STI区域之上，并且其中重叠的边界被放置成紧邻第二器件区域，以便在横向方向上引起其沟道区域的第一应力。版权所有（C）2009，JPO＆INPIT

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