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1. 发明公开

EP4287505A3 RECONFIGURABLE CRYSTAL OSCILLATOR AND METHOD FOR RECONFIGURING CRYSTAL OSCILLATOR 审中-实审
公开(公告)号：EP4287505A3
公开(公告)日：2024-02-28
申请号：EP23156874.2
申请日：2023-02-15
申请人： MediaTek Inc.
发明人： CHANG, Keng-Meng , LIU, Sen-You , WANG, Yao-Chi
IPC分类号： H03B5/36
摘要： A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.

2. 发明公开

EP3116130A1 METHOD FOR GENERATING A PLURALITY OF OSCILLATING SIGNALS WITH DIFFERENT PHASES AND ASSOCIATED CIRCUIT AND LOCAL OSCILLATOR 有权
标题翻译：方法生成具有不同的相位和相关电路与本振各种OSZILLERENDER SIGNALS
公开(公告)号：EP3116130A1
公开(公告)日：2017-01-11
申请号：EP16168938.5
申请日：2016-05-10
申请人： MediaTek Inc.
发明人： LEE, Yueh-Ting , WANG, Yao-Chi , TSENG, Sheng-Che
IPC分类号： H03L7/081 , H03B27/00
CPC分类号： H03B27/00 , H03K5/14 , H03K21/02 , H03K2005/00234 , H03L7/00 , H03L7/0812
摘要： A circuit (100) for generating a plurality of oscillating signals with different phases includes a frequency divider (120), a first delay chain (130_1), a second delay chain (130_2) and a calibration circuit (140). The frequency divider (120) is arranged for frequency dividing a first input signal and a second input signal to generate a first frequency-divided input signal and a second frequency-divided input signal. The first delay chain (130_1) is arranged for delaying the first frequency-divided input signal, and the second delay chain (130_2) is arranged for delaying the second frequency-divided input signal. The calibration circuit (140) is arranged for controlling delay amounts of the first delay chain (130_1) and the second delay chain (130_2) according to signals within the first delay chain (130_1) or the second delay chain (130_2); wherein output signals of a portion delay cells (210_1 -210_6, 220_1 -220_6) within the first delay chain (130_1) and the second delay chain (130_2) serve as the plurality of oscillating signals with different phases.
摘要翻译：一种用于生成具有不同相位的振荡信号的多个电路（100）包括一个分频器（120），第一延迟链（130_1），第二延迟链（130_2）和一个校准电路（140）。分频器（120）被布置用于分频的第一输入信号和第二输入信号，以产生一个第一分频输入信号和第二分频输入信号。第一延迟链（130_1）被布置用于延迟所述第一分频输入信号，和第二延迟链（130_2）被布置用于延迟所述第二分频输入信号。校准电路（140）被设置成用于控制雅丁第一延迟链（130_1）和第二延迟链（130_2）的延迟量到所述第一延迟链（130_1）或第二延迟链（130_2）内的信号; 在部分单元的延迟（210_1 -210_6，220_1 -220_6）第一延迟链内（130_1）和第二延迟链（130_2）的worin输出信号作为具有不同相位的振荡信号的多元性。

3. 发明公开

EP3396861A1 BIASED IMPEDANCE CIRCUIT, IMPEDANCE ADJUSTMENT CIRCUIT, AND ASSOCIATED SIGNAL GENERATOR 审中-实审
公开(公告)号：EP3396861A1
公开(公告)日：2018-10-31
申请号：EP18151357.3
申请日：2018-01-12
申请人： MediaTek Inc.
发明人： CHANG, Keng-Meng , WANG, Yao-Chi
IPC分类号： H03L7/06 , H03K19/00 , H03K5/159
CPC分类号： H03H11/30 , H03K5/159 , H03K19/0005 , H03K19/017545 , H03K19/21 , H03L1/00 , H03L1/022 , H03L7/06 , H03L7/0816 , H03L7/103 , H03L7/113 , H03L7/18 , H04B1/0475 , H04B1/1638 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

4. 发明公开

EP4287505A2 RECONFIGURABLE CRYSTAL OSCILLATOR AND METHOD FOR RECONFIGURING CRYSTAL OSCILLATOR 审中-实审
公开(公告)号：EP4287505A2
公开(公告)日：2023-12-06
申请号：EP23156874.2
申请日：2023-02-15
申请人： MediaTek Inc.
发明人： CHANG, Keng-Meng , LIU, Sen-You , WANG, Yao-Chi
IPC分类号： H03B5/36
摘要： A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.

5. 发明公开

EP3961919A1 CRYSTAL OSCILLATOR AND PHASE NOISE REDUCTION METHOD THEREOF 有权
公开(公告)号：EP3961919A1
公开(公告)日：2022-03-02
申请号：EP21175014.6
申请日：2021-05-20
申请人： MediaTek Inc.
发明人： CHEN, Chien-Wei , HSUEH, Yu-Li , CHANG, Keng-Meng , WANG, Yao-Chi
IPC分类号： H03B5/36
摘要： A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave.

6. 发明公开

EP3961918A1 CRYSTAL OSCILLATOR AND PHASE NOISE REDUCTION METHOD THEREOF 审中-实审
公开(公告)号：EP3961918A1
公开(公告)日：2022-03-02
申请号：EP21173900.8
申请日：2021-05-14
申请人： MediaTek Inc.
发明人： LIU, Sen-You , CHEN, Chien-Wei , CHANG, Keng-Meng , WANG, Yao-Chi
IPC分类号： H03B5/36
摘要： A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

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