专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3059762A3 WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION AND ASSOCIATED YIELD IMPROVEMENT METHOD 有权
标题翻译：带有多个SIDE并排布置CHIPS和相关收入增长的加工晶片层包装
公开(公告)号：EP3059762A3
公开(公告)日：2016-11-09
申请号：EP16155928.1
申请日：2016-02-16
申请人： MediaTek, Inc
发明人： CHEN, Yi-Hung , LIU, Yuan-Chin
IPC分类号： H01L25/065 , H01L25/00 , H01L23/538 , H01L23/00
CPC分类号： H01L24/02 , H01L23/538 , H01L23/5384 , H01L25/0655 , H01L25/50 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0401 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
摘要： A wafer-level package includes a plurality of dies (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1502, 1504_1-1504_2, 1602, 1604_1-1604_4) and a plurality of connection paths. The dies include at least a first die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4) and a second die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4). The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output pads arranged on the first side of the first die to input/output pads arranged on the first side of the second die, wherein adjacent input/output pads on the first side of the first die are connected to adjacent input/output pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out package or a chip on wafer on substrate package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

2. 发明公开

EP4376067A2 SEMICONDUCTOR PACKAGE STRUCTURE 审中-实审
公开(公告)号：EP4376067A2
公开(公告)日：2024-05-29
申请号：EP24168496.8
申请日：2020-03-12
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , LIU, Yuan-Chin
IPC分类号： H01L23/00
CPC分类号： H01L25/0655 , H01L23/66 , H01L2224/1210520130101 , H01L2924/1515120130101 , H01L2924/1531120130101 , H01L2924/1816220130101 , H01L2224/1622720130101 , H01L2224/7320420130101 , H01L2224/3222520130101 , H01L2224/9212520130101 , H01L2924/35120130101 , H01L2924/351120130101 , H01L2924/351220130101 , H01L2224/4813720130101 , H01L2224/7327720130101 , H01L2223/667720130101 , H01L2224/0410520130101 , H01L2223/668820130101 , H01L24/20 , H01L23/36 , H01L23/49816 , H01L23/5385 , H01L23/49822 , H01L23/562 , H01L23/3128
摘要： A semiconductor package structure (500, 700b) is provided. The semiconductor package structure (500, 700b) includes a substrate, a first semiconductor die (115a), and a second semiconductor die (115b). The substrate includes a first substrate partition (502a) and a second substrate partition (502b). The first substrate partition (502a) has a first wiring structure. The second substrate partition (502b) is adjacent to the first substrate partition (502a) and has a second wiring structure. The first substrate partition (502a) and the second substrate partition (502b) are surrounded by a first molding material (504). The first semiconductor die (115a) is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die (115b) is disposed over the substrate and electrically coupled to the second wiring structure. The semiconductor package structure (500b) further comprises a frame (113) surrounding the first substrate (502a) and the second substrate (502b), wherein the frame (113) is surrounded by the first molding material (504).

3. 发明公开

EP3709344A1 SEMICONDUCTOR PACKAGE STRUCTURE 有权
公开(公告)号：EP3709344A1
公开(公告)日：2020-09-16
申请号：EP20162559.7
申请日：2020-03-12
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , LIU, Yuan-Chin
IPC分类号： H01L23/31 , H01L25/065 , H01L23/66
摘要： A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

4. 发明公开

EP4376067A3 SEMICONDUCTOR PACKAGE STRUCTURE 审中-实审
公开(公告)号：EP4376067A3
公开(公告)日：2024-09-04
申请号：EP24168496.8
申请日：2020-03-12
申请人： MediaTek Inc.
发明人： LIN, Tzu-Hung , LIU, Yuan-Chin
IPC分类号： H01L23/538 , H01L23/00 , H01L23/498 , H01L25/065 , H01L23/31
CPC分类号： H01L25/0655 , H01L23/66 , H01L2224/1210520130101 , H01L2924/1515120130101 , H01L2924/1531120130101 , H01L2924/1816220130101 , H01L2224/1622720130101 , H01L2224/7320420130101 , H01L2224/3222520130101 , H01L2224/9212520130101 , H01L2924/35120130101 , H01L2924/351120130101 , H01L2924/351220130101 , H01L2224/4813720130101 , H01L2224/7327720130101 , H01L2223/667720130101 , H01L2224/0410520130101 , H01L2223/668820130101 , H01L24/20 , H01L23/36 , H01L23/49816 , H01L23/5385 , H01L23/49822 , H01L23/562 , H01L23/3128
摘要： A semiconductor package structure (500, 700b) is provided. The semiconductor package structure (500, 700b) includes a substrate, a first semiconductor die (115a), and a second semiconductor die (115b). The substrate includes a first substrate partition (502a) and a second substrate partition (502b). The first substrate partition (502a) has a first wiring structure. The second substrate partition (502b) is adjacent to the first substrate partition (502a) and has a second wiring structure. The first substrate partition (502a) and the second substrate partition (502b) are surrounded by a first molding material (504). The first semiconductor die (115a) is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die (115b) is disposed over the substrate and electrically coupled to the second wiring structure. The semiconductor package structure (500b) further comprises a frame (113) surrounding the first substrate (502a) and the second substrate (502b), wherein the frame (113) is surrounded by the first molding material (504).

5. 发明公开

EP3059762A2 WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION AND ASSOCIATED YIELD IMPROVEMENT METHOD 有权
标题翻译：带有多个SIDE并排布置CHIPS和相关收入增长的加工晶片层包装
公开(公告)号：EP3059762A2
公开(公告)日：2016-08-24
申请号：EP16155928.1
申请日：2016-02-16
申请人： MediaTek, Inc
发明人： CHEN, Yi-Hung , LIU, Yuan-Chin
IPC分类号： H01L25/065 , H01L25/00 , H01L23/538 , H01L23/00
CPC分类号： H01L24/02 , H01L23/538 , H01L23/5384 , H01L25/0655 , H01L25/50 , H01L2224/02371 , H01L2224/02373 , H01L2224/02379 , H01L2224/0401 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
摘要： A wafer-level package includes a plurality of dies (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1502, 1504_1-1504_2, 1602, 1604_1-1604_4) and a plurality of connection paths. The dies include at least a first die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4) and a second die (602_1-602_2, 702_1-702_4, 802_1-802_2, 902_1-902_4, 1002_1-1002_3, 1102_1-1102_2, 1202_1-1202_2, 1504_1-1504_2, 1604_1-1604_4). The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output pads arranged on the first side of the first die to input/output pads arranged on the first side of the second die, wherein adjacent input/output pads on the first side of the first die are connected to adjacent input/output pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out package or a chip on wafer on substrate package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.
摘要翻译：一种晶片级封装包括这种有多个（602_1-602_2，702_1-702_4，802_1-802_2，902_1-902_4，1002_1-1002_3，1102_1-1102_2，1202_1-1202_2，1502，1504_1-1504_2，1602，1604_1-1604_4 ）和连接路径复数。如此包括至少第一，第（602_1-602_2，702_1-702_4，802_1-802_2，902_1-902_4，1002_1-1002_3，1102_1-1102_2，1202_1-1202_2，1504_1-1504_2，1604_1-1604_4）和第二那（ 602_1-602_2，702_1-702_4，802_1-802_2，902_1-902_4，1002_1-1002_3，1102_1-1102_2，1202_1-1202_2，1504_1-1504_2，1604_1-1604_4）。的这个布置成并排侧的方式，与所述第一管芯的第一侧邻近于所述第二那的第一侧。连接路径连接设置在所述第一，到输入/输出焊盘布置在第二其中worin在第一的第一侧被连接到相邻的相邻的输入/输出焊盘的第一侧的第一侧的输入/输出焊盘经由路径仅单个层上的第二连接的所述第一侧的输入/输出焊盘。对于实施例，其中第一个是相同的第二对。对于另一实施例中，晶片级封装是一个集成的扇出包或上包晶片基底的芯片。对于又一实施例中，它被组装在晶片级封装执行网络切换功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式