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1. 发明授权

US08054149B2 Monolithic inductor 有权
标题翻译：单片电感
公开(公告)号：US08054149B2
公开(公告)日：2011-11-08
申请号：US11822230
申请日：2007-07-03
申请人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Yen-Ping Wang
发明人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Yen-Ping Wang
IPC分类号： H01F27/02 , H01F27/36 , H01F38/12 , H01F21/00 , H01F5/00
CPC分类号： H01F17/04 , H01F27/255 , H01F27/34 , H01F41/0246 , H01F2003/103 , H01F2017/046
摘要： This invention discloses a monolithic inductor including a body made by compressing a magnetic powder, a coil positioned in the body, and a permanent magnet positioned in the body and in a magnetic circuit formed by applying current to the coil. The monolithic inductor of this invention includes the magnetic body containing the permanent magnet and the coil. The permanent magnet in the magnetic circuit (path of magnetic flux lines) formed by applying current to the coil generates a reverse-bias magnetic field, thereby increasing the operating range of the magnetic body, the saturation current of the magnetic body, and the rated current of the inductor.
摘要翻译：本发明公开了一种单片电感器，其包括通过压缩磁粉制成的主体，位于本体中的线圈和位于本体中的永磁体以及通过向线圈施加电流而形成的磁路。本发明的单片电感器包括包含永磁体和线圈的磁体。通过向线圈施加电流而形成的磁路（磁通线路径）中的永磁体产生反向偏置磁场，从而增加磁体的工作范围，磁体的饱和电流和额定值电感电流。

2. 发明授权

US07429907B2 Power inductor with heat dissipating structure 有权
标题翻译：功率电感器具有散热结构
公开(公告)号：US07429907B2
公开(公告)日：2008-09-30
申请号：US11553936
申请日：2006-10-27
申请人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Ping-Feng Hsu , Yen-Ping Wang
发明人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Ping-Feng Hsu , Yen-Ping Wang
IPC分类号： H01F27/08
CPC分类号： H01F27/22 , H01F27/255 , H01F37/00
摘要： The present invention relates to a power inductor having a heat dissipating structure formed on the surface thereof, which comprises: at least a conducting wire; and a cladding, made of a magnetic material for wrapping the conductive wire, having the heat dissipating structure of embossed patterns formed on the surface thereof. Preferably, the embossed pattern can be a cone, a cuboid, a column, or the combination thereof. Moreover, the length of any edge or the diameter of any one of the embossed patterns is about 1%˜50% of that of the power inductor, and the height of any one of the embossed patterns is about 1%˜50% of the thickness of the power inductor.
摘要翻译：本发明涉及一种在其表面上形成有散热结构的功率电感器，其包括：至少导电线; 以及由用于缠绕导电线的磁性材料制成的包层，其具有形成在其表面上的压花图案的散热结构。优选地，压纹图案可以是锥体，长方体，柱或其组合。此外，任何一个压花图案的任何一个边缘或直径的长度为功率电感器的长度的约1％〜50％，并且任何一个压纹图案的高度为约1％〜50％功率电感的厚度。

3. 发明申请

US20080157912A1 Monolithic inductor 有权
标题翻译：单片电感
公开(公告)号：US20080157912A1
公开(公告)日：2008-07-03
申请号：US11822230
申请日：2007-07-03
申请人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Yen-Ping Wang
发明人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Yen-Ping Wang
IPC分类号： H01F5/00 , H01F27/24
CPC分类号： H01F17/04 , H01F27/255 , H01F27/34 , H01F41/0246 , H01F2003/103 , H01F2017/046
摘要： This invention discloses a monolithic inductor including a body made by compressing a magnetic powder, a coil positioned in the body, and a permanent magnet positioned in the body and in a magnetic circuit formed by applying current to the coil. The monolithic inductor of this invention includes the magnetic body containing the permanent magnet and the coil. The permanent magnet in the magnetic circuit (path of magnetic flux lines) formed by applying current to the coil generates a reverse-bias magnetic field, thereby increasing the operating range of the magnetic body, the saturation current of the magnetic body, and the rated current of the inductor.
摘要翻译：本发明公开了一种单片电感器，其包括通过压缩磁粉制成的主体，位于本体中的线圈和位于本体中的永磁体以及通过向线圈施加电流而形成的磁路。本发明的单片电感器包括包含永磁体和线圈的磁体。通过向线圈施加电流而形成的磁路（磁通线路径）中的永磁体产生反向偏置磁场，从而增加磁体的工作范围，磁体的饱和电流和额定值电感电流。

4. 发明授权

US06569346B1 Ferrite with high permeability and high dielectric constant and method for making the same 有权
标题翻译：具有高磁导率和高介电常数的铁氧体及其制造方法
公开(公告)号：US06569346B1
公开(公告)日：2003-05-27
申请号：US10029236
申请日：2001-12-28
申请人： Mean-Jue Tung , Yu-Ting Huang , Yen-Ping Wang
发明人： Mean-Jue Tung , Yu-Ting Huang , Yen-Ping Wang
IPC分类号： C04B3564
CPC分类号： C04B35/6262 , C04B35/265 , C04B35/2658 , C04B35/2666 , C04B35/2683 , C04B35/2691 , C04B2235/3203 , C04B2235/3206 , C04B2235/3232 , C04B2235/3262 , C04B2235/3274 , C04B2235/3279 , C04B2235/3281 , C04B2235/3284 , C04B2235/5445 , C04B2235/608 , H01F1/344 , H01F41/0246 , H01F2017/0066
摘要： A ferrite with a high permeability and a high dielectric constant is introduced. Raw material powders, such as TiO2, Fe2O3 and the oxide of Mn, Ni, Cu, Mg, Li or Zn is prepared and combined in the proportion Tix(MFe2O4+2x/y)y, where x+y=1 and 0
摘要翻译：引入具有高磁导率和高介电常数的铁氧体。制备原料粉末如TiO2，Fe2O3和Mn，Ni，Cu，Mg，Li或Zn的氧化物，并以Tix（MFe2O4 + 2x / y）y的比例组合，其中x + y = 1和0 < x <1。 M是选自Mn，Ni，Cu和Zn中的任何一种金属的混合物。可以根据实际需要调整x和y之间的比例，以获得具有不同渗透率和介电常数的铁氧体。铁氧体可以同时成为电子元件中的磁性材料和电介质材料。这可以避免现有技术中由于两种不同材料的烧结而引起的可能的缺陷。

5. 发明申请

US20070152792A1 Power Inductor with Heat Dissipating Structure 有权
标题翻译：具有散热结构的功率电感器
公开(公告)号：US20070152792A1
公开(公告)日：2007-07-05
申请号：US11553936
申请日：2006-10-27
申请人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Ping-Feng Hsu , Yen-Ping Wang
发明人： Mean-Jue Tung , Wen-Song Ko , Yu-Ting Huang , Ping-Feng Hsu , Yen-Ping Wang
IPC分类号： H01F27/08
CPC分类号： H01F27/22 , H01F27/255 , H01F37/00
摘要： The present invention relates to a power inductor having a heat dissipating structure formed on the surface thereof, which comprises: at least a conducting wire; and a cladding, made of a magnetic material for wrapping the conductive wire, having the heat dissipating structure of embossed patterns formed on the surface thereof. Preferably, the embossed pattern can be a cone, a cuboid, a column, or the combination thereof. Moreover, the length of any edge or the diameter of any one of the embossed patterns is about 1%˜50% of that of the power inductor, and the height of any one of the embossed patterns is about 1%˜50% of the thickness of the power inductor.
摘要翻译：本发明涉及一种在其表面上形成有散热结构的功率电感器，其包括：至少导电线; 以及由用于缠绕导电线的磁性材料制成的包层，其具有形成在其表面上的压花图案的散热结构。优选地，压纹图案可以是锥体，长方体，柱或其组合。此外，任何一个压花图案的任何一个边缘或直径的长度为功率电感器的长度的约1％〜50％，并且任何一个压纹图案的高度为约1％〜50％功率电感的厚度。

6. 发明申请

US20110006828A1 DIFFERENTIAL TYPE LEVEL SHIFTER 审中-公开
标题翻译：差分式水平变换器
公开(公告)号：US20110006828A1
公开(公告)日：2011-01-13
申请号：US12500874
申请日：2009-07-10
申请人： Pei-Yuan Chen , Chu-Chiao Yu , Yen-Ping Wang
发明人： Pei-Yuan Chen , Chu-Chiao Yu , Yen-Ping Wang
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： This patent discloses a differential type level shifter, comprising: a differential pair of transistors, having a pair of gate terminals, a pair of drain terminals and a common source terminal, with the pair of gate terminals coupled to a first clock signal and a second clock signal; a current source, coupled between the common source terminal and a reference ground, used to provide a bias current; and a pair of loading resistors, having a common end and a pair of output ends, with the common end coupled to a power line, the pair of output ends coupled to the pair of drain terminals; wherein the pair of drain terminals are used to generate a set signal and a reset signal in response to the first clock signal and the second clock signal.
摘要翻译：该专利公开了一种差分电平移位器，包括：具有一对栅极端子，一对漏极端子和公共源极端子的差分对晶体管，其中该对栅极端子耦合到第一时钟信号和第二时钟信号时钟信号; 耦合在公共源极端子和参考地之间的电流源，用于提供偏置电流; 以及一对负载电阻器，具有公共端和一对输出端，其共同端耦合到电力线，所述一对输出端耦合到所述一对漏极端子; 其中所述一对漏极端子用于响应于所述第一时钟信号和所述第二时钟信号而产生置位信号和复位信号。

7. 发明授权

US07867860B2 Strained channel transistor formation 有权
标题翻译：应变通道晶体管形成
公开(公告)号：US07867860B2
公开(公告)日：2011-01-11
申请号：US10897563
申请日：2004-07-23
申请人： Yi-Chun Huang , Yen-Ping Wang , Chih-Hsin Ko
发明人： Yi-Chun Huang , Yen-Ping Wang , Chih-Hsin Ko
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L29/41783 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7842 , H01L29/7848 , Y10S438/938
摘要： A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.
摘要翻译：提供了一个应变通道晶体管。应变通道晶体管包括由第一材料形成的衬底。由第二材料构成的源极区域形成在基板的第一凹部中，并且由第二材料构成的漏极区域形成在基板的第二凹部中。由第一材料形成的应变通道区域在源区和漏区之间。形成在通道区域上方的栅极叠层包括覆盖栅极电介质的栅电极。沿着栅电极的侧壁形成的栅极间隔物覆盖至少一个所述源极区域和漏极区域的一部分。可以在第二材料上形成覆盖层，并且源极和漏极区域可以被硅化。

8. 发明授权

US07498641B2 Partial replacement silicide gate 有权
标题翻译：局部替代硅化物门
公开(公告)号：US07498641B2
公开(公告)日：2009-03-03
申请号：US11117153
申请日：2005-04-28
申请人： Chih-Hao Wang , Yen-Ping Wang , Chenming Hu
发明人： Chih-Hao Wang , Yen-Ping Wang , Chenming Hu
IPC分类号： H01L23/62
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer. A top layer is formed over the dielectric layer. The gate dielectric, the silicon-containing layer, the dielectric layer, and the top layer are patterned into a gate stack. A spacer is formed along an edge of the gate stack. The top layer and the dielectric layer are removed. A metal layer is deposited on the silicon-containing layer and silicided.
摘要翻译：提出了一种形成均匀栅极硅化物厚度的完全硅化物栅的方法。在衬底上形成栅极电介质。在栅极电介质上形成含硅层。在含硅层上方形成介电层。在电介质层上形成顶层。栅极电介质，含硅层，电介质层和顶层被图案化成栅叠层。沿栅极堆叠的边缘形成间隔物。去除顶层和介电层。将金属层沉积在含硅层上并硅化。

9. 发明授权

US07018883B2 Dual work function gate electrodes 有权
标题翻译：双功能门电极
公开(公告)号：US07018883B2
公开(公告)日：2006-03-28
申请号：US10839430
申请日：2004-05-05
申请人： Chih-Hao Wang , Tzung-Lin Li , Yen-Ping Wang , Chun-Yen Chang
发明人： Chih-Hao Wang , Tzung-Lin Li , Yen-Ping Wang , Chun-Yen Chang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. The metal layer is heated to form a metal gate electrode over the first region, and the metal layer and the semiconductor layer are collectively heated to form a composite metal gate electrode over the second region.
摘要翻译：在一个实施例中，制造晶体管栅极的方法包括在衬底的第一和第二区域上形成金属层，其中第一和第二区域分别具有不同的第一和第二掺杂剂类型。在第二区域的至少一部分上形成半导体层。金属层被加热以在第一区域上形成金属栅电极，并且金属层和半导体层被共同加热，以在第二区域上形成复合金属栅电极。

10. 发明申请

US20140002140A1 LEVEL SHIFTER CAPABLE OF PULSE FILTERING AND BRIDGE DRIVER USING THE SAME 审中-公开
标题翻译：使用脉冲滤波和桥式驱动器的水平变压器
公开(公告)号：US20140002140A1
公开(公告)日：2014-01-02
申请号：US13535950
申请日：2012-06-28
申请人： Yen-Ping Wang
发明人： Yen-Ping Wang
IPC分类号： H03K3/00 , H03L5/00
CPC分类号： H03K17/063 , H03K3/356
摘要： A level shifter capable of pulse filtering and a bridge driver using the same, the level shifter capable of pulse filtering being used for up shifting a first clock signal and a second clock signal to provide a set signal and a reset signal, and for preventing noise on the first clock signal or on the second clock signal from altering the states of the set signal and the reset signal.
摘要翻译：能够进行脉冲滤波的电平移位器和使用其的桥式驱动器，能够进行脉冲滤波的电平移位器用于上变频第一时钟信号和第二时钟信号以提供置位信号和复位信号，并且用于防止噪声在第一时钟信号或第二时钟信号上改变设置信号和复位信号的状态。

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