专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050187787A1 Method for payer access to medical image data 审中-公开
标题翻译：支付者访问医学图像数据的方法
公开(公告)号：US20050187787A1
公开(公告)日：2005-08-25
申请号：US10782902
申请日：2004-02-23
申请人： Max Tomlinson , Tsuneo Imai , Stanley Shapiro , Richard Bennett , C. Tomlinson , Alexander Joffe
发明人： Max Tomlinson , Tsuneo Imai , Stanley Shapiro , Richard Bennett , C. Tomlinson , Alexander Joffe
IPC分类号： G06Q30/00 , G06Q50/00 , G06F17/60
CPC分类号： G06Q30/06 , G06Q50/22
摘要： A business method provides access to digital medical image data generated by up to a plurality of imaging facilities to a payer. The business method includes receiving digital medical image data generated by the imaging facilities using a gateway at each imaging facility. The received-digital medical image data is transmitted from the gateway to a central server via a network and stored at the central server. The payer is then provided access to the stored digital medical image data via the network for a fee.
摘要翻译：业务方法提供对由多个成像设施产生的数字医学图像数据的访问给付款者。业务方法包括在每个成像设施处使用网关接收由成像设备生成的数字医学图像数据。接收数字医学图像数据经由网络从网关发送到中央服务器，并存储在中央服务器。然后，付款人通过网络提供对存储的数字医疗图像数据的访问费用。

2. 发明申请

US20050197860A1 Data management system 审中-公开
标题翻译：数据管理系统
公开(公告)号：US20050197860A1
公开(公告)日：2005-09-08
申请号：US10782904
申请日：2004-02-23
申请人： Alexander Joffe , Samuel Coroniti , Daniel Wilson , C. Tomlinson , Max Tomlinson
发明人： Alexander Joffe , Samuel Coroniti , Daniel Wilson , C. Tomlinson , Max Tomlinson
IPC分类号： G06F17/60
CPC分类号： G06Q50/22 , G16H10/60
摘要： A data management system includes a server system and a data forwarding unit for forwarding data to the server system via a public network. The server system includes a storage system for storing data, an information system for storing information on data managed by the data management system, and a plurality of interfaces for accessing the server system via the public network. When the data forwarding unit receives data, identification information on the received data is sent to the information system via one of the plurality of interfaces selected by the data forwarding unit in accordance with a set of predetermined rules. In response to receiving identification information from the data forwarding unit, the information system sends communication information for one of the plurality of interfaces selected by the information system in accordance with a set of predetermined rules. Using the communication information, the data forwarding unit forwards the received data to the storage system for storage via the interface selected by the information system.
摘要翻译：数据管理系统包括服务器系统和数据转发单元，用于经由公共网络将数据转发到服务器系统。服务器系统包括用于存储数据的存储系统，用于存储由数据管理系统管理的数据的信息的信息系统，以及用于经由公共网络访问服务器系统的多个接口。当数据转发单元接收数据时，根据一组预定规则，通过数据转发单元选择的多个接口中的一个，将接收到的数据的识别信息发送到信息系统。响应于从数据转发单元接收到识别信息，信息系统根据一组预定规则发送由信息系统选择的多个接口之一的通信信息。使用通信信息，数据转发单元经由信息系统选择的接口将接收到的数据转发到存储系统进行存储。

3. 发明申请

US20080320485A1 Logic for Synchronizing Multiple Tasks at Multiple Locations in an Instruction Stream 失效
标题翻译：用于在指令流中的多个位置同步多个任务的逻辑
公开(公告)号：US20080320485A1
公开(公告)日：2008-12-25
申请号：US12201385
申请日：2008-08-29
申请人： Alexander Joffe , Asad Khamisy
发明人： Alexander Joffe , Asad Khamisy
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/52
摘要： Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).
摘要翻译：基于一个或多个路径的初始确定，协处理器（提供到存储器的接口）中的逻辑（也称为“同步逻辑”）从多个任务中的每一个接收信号（称为“声明”）（也称为“代码路径”）在任务可能遵循的指令流（例如源自高级软件程序或低级微代码）中。一旦任务（也被称为“禁用”任务）声明其缺少访问共享数据的需要，同步逻辑允许共享数据被其他指示（也称为“需要”的任务）访问，这些任务已经表明了他们的需要访问相同。此外，同步逻辑还允许在当前任务完成对共享数据的访问时由其他有需要的任务访问共享数据（假设当前任务也是有需要的任务）。

4. 发明授权

US07155718B1 Method and apparatus to suspend and resume on next instruction for a microcontroller 失效
标题翻译：微控制器的下一条指令暂停和恢复的方法和装置
公开(公告)号：US07155718B1
公开(公告)日：2006-12-26
申请号：US10117394
申请日：2002-04-04
申请人： Alexander Joffe
发明人： Alexander Joffe
IPC分类号： G06F7/00
CPC分类号： G06F9/3851 , G06F9/3824
摘要： In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a resource is not ready, unnecessary attempts to execute subsequent instruction can be avoided. If a processor register has not yet been loaded and the next instruction attempts to use that register, the task will suspend. A task can also be suspended by incorporating a computer instruction that suspends the task after execution. A task can also be suspended by utilizing resources that provide one or more suspend indications. Such suspend indications can include a “suspend-and-resume-on-current-instruction” indication that suspends the current task and leaves the program counter (PC) value pointing to the current instruction or can include a “suspend-and-resume-on-next-instruction” indication that suspends the current task after completion of the current instruction and advances the program counter (PC) value to point to the next instruction. When the task becomes active again, the task begins execution at the instruction pointed to by the PC.
摘要翻译：在包括至少一个微控制器的计算机系统中，通过在执行诸如来自外部存储器指令的加载寄存器指令之类的特定指令之后暂停任务，或者当资源未就绪时，可以避免执行后续指令的不必要的尝试。如果处理器寄存器尚未加载，并且下一条指令尝试使用该寄存器，则任务将暂停。还可以通过并入执行后暂停任务的计算机指令来暂停任务。也可以通过利用提供一个或多个挂起指示的资源来暂停任务。这种暂停指示可以包括暂停当前任务并使程序计数器（PC）值指向当前指令的“暂停和恢复当前指令”指示，或者可以包括“挂起和恢复 - 下一条指令“指示，在当前指令完成后暂停当前任务，并将程序计数器（PC）值提前指向下一条指令。当任务再次变为活动状态时，任务开始执行PC指示的指令。

5. 发明授权

US06415354B1 Pipelined methods and apparatus for weight selection and content addressable memory searches 有权
标题翻译：用于权重选择和内容可寻址存储器搜索的流水线方法和装置
公开(公告)号：US06415354B1
公开(公告)日：2002-07-02
申请号：US09354684
申请日：1999-07-15
申请人： Alexander Joffe , Oran Uzrad-Nali , Simon H. Milner
发明人： Alexander Joffe , Oran Uzrad-Nali , Simon H. Milner
IPC分类号： G06F1318
CPC分类号： G11C15/00
摘要： When a search key is supplied to a content addressable memory (CAM), the CAM signals indicate which CAM entries have matched the key. These signals are provided to a weight array to select the entry of the highest priority. Each entry's priority is indicated by a weight in the weight array. The weight array processing is pipelined. In pipeline stage 0, the most significant bits (bits 0) of the weights are examined, and the highest priorities are selected based on the most significant bits. At pipeline stage 1, the next most significant bits (bits 1) are examined, and so on.
摘要翻译：当搜索关键字提供给内容可寻址存储器（CAM）时，CAM信号指示哪些CAM条目与密钥相匹配。这些信号被提供给权重阵列以选择最高优先级的条目。每个条目的优先级由权重数组中的权重表示。重量阵列处理是流水线的。在流水线阶段0中，检查权重的最高有效位（位0），并且基于最高有效位选择最高优先级。在流水线阶段1，检查下一个最高有效位（位1），依此类推。

6. 发明授权

US06307860B1 Systems and methods for data transformation and transfer in networks 失效
标题翻译：网络数据转换和传输的系统和方法
公开(公告)号：US06307860B1
公开(公告)日：2001-10-23
申请号：US09055044
申请日：1998-04-03
申请人： Alexander Joffe , Dmitry Vyshetsky
发明人： Alexander Joffe , Dmitry Vyshetsky
IPC分类号： H04L1228
CPC分类号： H04L49/3081 , H04L12/5601 , H04L49/1553 , H04L49/255 , H04L49/351 , H04L2012/5652 , H04L2012/5658 , H04L2012/5665 , H04Q11/0478
摘要： A processor system suitable to provide an interface between networks includes a software programmable processor and a channel processor that receives data from a network and transforms data at commands from the software programmable processor. The channel can execute only a few simple commands, but these commands are sufficient for a wide range of systems. The commands include (1) a command to transmit received data, perhaps skipping some data; and (2) a command to transmit data specified by the command itself rather than the received data. The channel is fast, simple and inexpensive.
摘要翻译：适于提供网络之间的接口的处理器系统包括软件可编程处理器和从网络接收数据并以来自软件可编程处理器的命令转换数据的通道处理器。该通道只能执行几个简单的命令，但这些命令对于广泛的系统是足够的。命令包括（1）发送接收数据的命令，可能跳过一些数据; 和（2）用于发送由命令本身指定的数据而不是接收到的数据的命令。频道快速，简单，便宜。

7. 发明授权

US5359568A FIFO memory system 失效
标题翻译： FIFO存储器系统
公开(公告)号：US5359568A
公开(公告)日：1994-10-25
申请号：US72643
申请日：1993-06-03
申请人： Aviel Livay , Ricardo Berger , Alexander Joffe
发明人： Aviel Livay , Ricardo Berger , Alexander Joffe
IPC分类号： G06F5/06 , G11C7/00 , G06F12/00
CPC分类号： G06F5/065 , G06F2205/064 , G06F2205/066
摘要： This invention relates to a FIFO memory system (10) comprising a plurality of FIFO memories (20) for handling transmission queues in a serial digital communication system. The memory system comprises a plurality of blocks of memory (20a-c, 21a-e), each of the plurality of FIFO memories being assigned a block (20a) of the plurality of blocks of memory, the unassigned blocks of memory forming a block pool (21a-e). The memory system further comprises memory management means (LLT, PT) for adding at least one of the unassigned blocks of memory from the block pool to a FIFO memory on writing to the FIFO memory whereby the size of the FIFO memory is selectably variable, and for returning a block of memory from a FIFO memory to the block pool once the contents of the block of memory have been read.
摘要翻译：本发明涉及一种包括用于处理串行数字通信系统中的传输队列的多个FIFO存储器（20）的FIFO存储器系统（10）。存储器系统包括多个存储块（20a-c，21a-e），多个FIFO存储器中的每一个被分配多个存储器块的块（20a），未分配的存储器块形成块池（21a-e）。存储器系统还包括存储器管理装置（LLT，PT），用于在写入FIFO存储器时将来自块池的未分配存储器块中的至少一个从FIFO存储器加到FIFO存储器中，由此FIFO存储器的大小是可选择地可变的，以及一旦已经读取存储器块的内容，则将一块存储器从FIFO存储器返回到块池。

8. 发明授权

US08001547B2 Logic for synchronizing multiple tasks at multiple locations in an instruction stream 失效
标题翻译：用于在指令流中的多个位置同步多个任务的逻辑
公开(公告)号：US08001547B2
公开(公告)日：2011-08-16
申请号：US12201385
申请日：2008-08-29
申请人： Alexander Joffe , Asad Khamisy
发明人： Alexander Joffe , Asad Khamisy
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/52
摘要： Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).
摘要翻译：基于一个或多个路径的初始确定，协处理器（提供到存储器的接口）中的逻辑（也称为“同步逻辑”）从多个任务中的每一个接收信号（称为“声明”）（也称为“代码路径”）在任务可能遵循的指令流（例如源自高级软件程序或低级微代码）中。一旦任务（也被称为“禁用”任务）声明其缺少访问共享数据的需要，同步逻辑允许共享数据被其他指示（也称为“需要”的任务）访问，这些任务已经表明了他们的需要访问相同。此外，同步逻辑还允许在当前任务完成对共享数据的访问时由其他有需要的任务访问共享数据（假设当前任务也是有需要的任务）。

9. 发明申请

US20090282408A1 SYSTEMS AND METHODS FOR MULTI-TASKING, RESOURCE SHARING, AND EXECUTION OF COMPUTER INSTRUCTIONS 有权
标题翻译：用于多种任务，资源共享和计算机指令执行的系统和方法
公开(公告)号：US20090282408A1
公开(公告)日：2009-11-12
申请号：US12504313
申请日：2009-07-16
申请人： Alexander Joffe , Dmitry Vyshetsky
发明人： Alexander Joffe , Dmitry Vyshetsky
IPC分类号： G06F9/46 , H04L12/00
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/461 , G06F9/52 , G06F2209/507
摘要： In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.
摘要翻译：在多任务流水线处理器中，连续的指令由不同的任务执行，消除了当前一条指令无法完成时清除随后指令的指令执行流水线的需要。任务不共享存储任务特定值的寄存器，因此在新任务计划执行时不需要保存或加载寄存器。如果指令访问不可用资源，则指令将被暂停，从而允许执行其他任务的指令，直到资源变为可用。任务调度由硬件执行; 不需要操作系统。提供简单的技术来同步不同任务之间的共享资源访问。

10. 发明授权

US06625122B1 Selection of data for network transmission 有权
标题翻译：选择网络传输数据
公开(公告)号：US06625122B1
公开(公告)日：2003-09-23
申请号：US09449146
申请日：1999-11-24
申请人： Alexander Joffe
发明人： Alexander Joffe
IPC分类号： H04L1226
CPC分类号： H04L49/3081 , H04L2012/5679 , H04L2012/5681 , H04Q11/0478
摘要： Data flows are queued in an active queue (160.0) waiting for transmission. In each time slot, one data flow can be dequeued from the head of the active queue, and a data unit can be transmitted on the data flow. Then the data flow is placed in a queue “i” which is one of the queues 1, 2, . . . N. Data flows are transferred from queue “i” to the active queue once in every 2i time slots. When a data flow is dequeued from the active queue and transferred to queue i, the queue number “i” is determined as i=log &Dgr;, rounded to an integer, where A is the number of time slots in which one data unit must be transmitted from the data flow in order to meet a data flow bandwidth parameter. If the data flow has waited for “d” time slots in the active queue before being dequeued, then i=log (&Dgr;−d), rounded to an integer.
摘要翻译：数据流在等待传输的活动队列（160.0）中排队。在每个时隙中，一个数据流可以从活动队列的头部出队，并且数据单元可以在数据流上传输。然后将数据流放置在作为队列1,2之一的队列“i”中。。。数据流从队列“i”到每2个时隙一次传送到活动队列。当数据流从活动队列出队并被传送到队列i时，队列号“i”被确定为i = log Delta，舍入为整数，其中A是一个数据单元必须的时隙数从数据流传输，以满足数据流带宽参数。如果数据流在出队之前等待了活动队列中的“d”个时隙，则i = log（Δ-d），舍入为整数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式