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1. 发明申请

US20070278693A1 METALLIZATION LAYER OF A SEMICONDUCTOR DEVICE HAVING DIFFERENTLY THICK METAL LINES AND A METHOD OF FORMING THE SAME 有权
标题翻译：具有不同金属线的半导体器件的金属化层及其形成方法
公开(公告)号：US20070278693A1
公开(公告)日：2007-12-06
申请号：US11619235
申请日：2007-01-03
申请人： Matthias Lehr , Matthias Schaller , Carsten Peters
发明人： Matthias Lehr , Matthias Schaller , Carsten Peters
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76817 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L21/76826 , H01L21/76835 , H01L21/7684 , H01L23/5283
摘要： A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.
摘要翻译：半导体器件包括在特定金属化层中的金属线，其具有不同的厚度，因此在不同器件区域中具有不同的电阻率。以这种方式，在装置的高密度区域中，可以提供厚度减小的金属线，以便符合实现相邻金属线之间的最小间距的工艺要求，而在其它区域中，对于最小间距具有较小的关键限制与常规策略相比，在减小的横向尺寸下可以获得降低的电阻率。为此，金属化层的电介质材料可以在形成相应的沟槽之前被适当地图案化，或者可以选择性地调整电介质材料的蚀刻行为以获得不同深度的沟槽。

2. 发明授权

US07592258B2 Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same 有权
标题翻译：具有不同厚度金属线的半导体器件的金属化层及其形成方法
公开(公告)号：US07592258B2
公开(公告)日：2009-09-22
申请号：US11619235
申请日：2007-01-03
申请人： Matthias Lehr , Matthias Schaller , Carsten Peters
发明人： Matthias Lehr , Matthias Schaller , Carsten Peters
IPC分类号： H01L21/4763
CPC分类号： H01L21/76817 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L21/76826 , H01L21/76835 , H01L21/7684 , H01L23/5283
摘要： A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.
摘要翻译：半导体器件包括在特定金属化层中的金属线，其具有不同的厚度，因此在不同器件区域中具有不同的电阻率。以这种方式，在装置的高密度区域中，可以提供厚度减小的金属线，以便符合实现相邻金属线之间的最小间距的工艺要求，而在其它区域中，对于最小间距具有较小的关键限制与常规策略相比，在减小的横向尺寸下可以获得降低的电阻率。为此，金属化层的电介质材料可以在形成相应的沟槽之前被适当地图案化，或者可以选择性地调整电介质材料的蚀刻行为以获得不同深度的沟槽。

3. 发明授权

US08062982B2 High yield plasma etch process for interlayer dielectrics 有权
标题翻译：用于层间电介质的高产量等离子体蚀刻工艺
公开(公告)号：US08062982B2
公开(公告)日：2011-11-22
申请号：US11867972
申请日：2007-10-05
申请人： Daniel Fischer , Matthias Schaller , Matthias Lehr , Kornelia Dittmar
发明人： Daniel Fischer , Matthias Schaller , Matthias Lehr , Kornelia Dittmar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/0209 , H01L21/31138
摘要： A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer.
摘要翻译：提供了一种用于半导体器件的层间电介质层的高产量等离子体蚀刻工艺，根据其实施例，用含氮等离子体蚀刻电介质层。以这种方式，避免或显着减少在基板的背面斜面上形成聚合物。通过后蚀刻处理可以将位于后侧斜面处的剩余聚合物原位移除。此外，提供了一种等离子体蚀刻装置，其包括腔室，用于接收衬底的衬底接收空间，用于在腔室中产生等离子体的等离子体发生器和用于调节衬底接收空间的外周区域处的温度的温度调节器，从而最小化晶片斜面处的温度梯度。

4. 发明申请

US20080202685A1 HIGH YIELD PLASMA ETCH PROCESS FOR INTERLAYER DIELECTRICS 有权
标题翻译：用于中间层电介质的高等离子体等离子体蚀刻工艺
公开(公告)号：US20080202685A1
公开(公告)日：2008-08-28
申请号：US11867972
申请日：2007-10-05
申请人： Daniel Fischer , Matthias Schaller , Matthias Lehr , Kornelia Dittmar
发明人： Daniel Fischer , Matthias Schaller , Matthias Lehr , Kornelia Dittmar
IPC分类号： H01L21/3065 , G06F19/00 , H01L21/67
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/0209 , H01L21/31138
摘要： A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer.
摘要翻译：提供了一种用于半导体器件的层间电介质层的高产量等离子体蚀刻工艺，根据其实施例，用含氮等离子体蚀刻电介质层。以这种方式，避免或显着减少在基板的背面斜面上形成聚合物。通过后蚀刻处理可以将位于后侧斜面处的剩余聚合物原位移除。此外，提供了一种等离子体蚀刻装置，其包括腔室，用于接收衬底的衬底接收空间，用于在腔室中产生等离子体的等离子体发生器和用于调节衬底接收空间的外周区域处的温度的温度调节器，从而最小化晶片斜面处的温度梯度。

5. 发明申请

US20080081480A1 METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON NITRIDE LAYERS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中用于降低硅氮化物层的方式减少耐药性的方法
公开(公告)号：US20080081480A1
公开(公告)日：2008-04-03
申请号：US11742878
申请日：2007-05-01
申请人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
发明人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.
摘要翻译：通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒不同类型的内在应力。

6. 发明申请

US20070120264A1 A SEMICONDUCTOR HAVING A COPPER-BASED METALLIZATION STACK WITH A LAST ALUMINUM METAL LINE LAYER 审中-公开
标题翻译：具有基于铜的金属叠层的半导体与最后的铝金属线层
公开(公告)号：US20070120264A1
公开(公告)日：2007-05-31
申请号：US11530071
申请日：2006-09-08
申请人： Matthias Lehr , Matthias Schaller , Tobias Letz
发明人： Matthias Lehr , Matthias Schaller , Tobias Letz
IPC分类号： H01L23/48
CPC分类号： H01L23/53228 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05083 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： By replacing, in an otherwise copper-based metallization stack, copper with aluminum in the very last metal line layer, the respective terminal metal layer of conventional semiconductor devices may be omitted. Consequently, an enormous gain in production cost savings may be achieved, since a plurality of process steps may be omitted, while, on the other hand, substantially no performance degradation may result.
摘要翻译：通过在最后的金属线层中用另外的铜基金属化叠层代替铜，可以省略常规半导体器件的各个端子金属层。因此，可以实现生产成本节约的巨大增益，因为可以省略多个处理步骤，而另一方面基本上不会导致性能下降。

7. 发明授权

US07550396B2 Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device 有权
标题翻译：用于在半导体器件中的氮化硅层的图案化期间减少抗蚀剂中毒的方法
公开(公告)号：US07550396B2
公开(公告)日：2009-06-23
申请号：US11742878
申请日：2007-05-01
申请人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
发明人： Kai Frohberg , Volker Grimm , Sven Mueller , Matthias Lehr , Ralf Richter , Jochen Klais , Martin Mazur , Heike Salz , Joerg Hohage , Matthias Schaller
IPC分类号： H01L21/461
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.
摘要翻译：通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒不同类型的内在应力。

8. 发明授权

US09450042B2 Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating same 有权
标题翻译：具有金属绝缘体金属（MIM）电容器的集成电路及其制造方法
公开(公告)号：US09450042B2
公开(公告)日：2016-09-20
申请号：US13567853
申请日：2012-08-06
申请人： Matthias Lehr
发明人： Matthias Lehr
IPC分类号： H01L21/02 , H01L21/8242 , H01L49/02 , H01L23/522
CPC分类号： H01L28/75 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface.
摘要翻译：提供了具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路和用于制造这种集成电路的方法。在一个实施例中，集成电路包括覆盖半导体衬底的电介质材料层。表面调理层覆盖在介电材料层上。此外，在表面调理层上直接形成金属层。 MIM电容器位于金属层上。 MIM电容器包括直接在金属层上形成的具有平滑上表面的第一导电层，直接形成在第一导电层的平滑上表面上的绝缘体层，以及直接形成在绝缘体层上的平滑的第二导电层，下表面。

9. 发明授权

US08482123B2 Stress reduction in chip packaging by using a low-temperature chip-package connection regime 有权
标题翻译：通过使用低温芯片封装连接方式降低芯片封装的压力
公开(公告)号：US08482123B2
公开(公告)日：2013-07-09
申请号：US13179643
申请日：2011-07-11
申请人： Michael Grillberger , Matthias Lehr , Thomas Werner
发明人： Michael Grillberger , Matthias Lehr , Thomas Werner
IPC分类号： H01L23/48
CPC分类号： H01L23/49811 , H01L21/4853 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05571 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11622 , H01L2224/11825 , H01L2224/13007 , H01L2224/13011 , H01L2224/13012 , H01L2224/13014 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13186 , H01L2224/1319 , H01L2224/1357 , H01L2224/13644 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17517 , H01L2224/17519 , H01L2224/81141 , H01L2224/81345 , H01L2224/81898 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.
摘要翻译：半导体芯片和封装基板可以通过在半导体芯片和封装基板中提供适当形状的互补的接触结构，在形式闭合的基础上直接连接。因此，可能不再需要焊料材料，因此可以避免组装过程中的任何升高的温度，这常常会导致显着的应力，从而造成损坏，特别是在非常复杂的金属化系统中。

10. 发明授权

US08392573B2 Transport of customer flexibility changes in a multi-tenant environment 有权
标题翻译：在多租户环境中运输客户灵活性变化
公开(公告)号：US08392573B2
公开(公告)日：2013-03-05
申请号：US12847746
申请日：2010-07-30
申请人： Matthias Lehr , Stefan Baeuerle , Karsten Fanghaenel , Bernhard Thimmel , Uwe Schlarb , Olaf Meincke , Volker Driesen , Juergen Specht
发明人： Matthias Lehr , Stefan Baeuerle , Karsten Fanghaenel , Bernhard Thimmel , Uwe Schlarb , Olaf Meincke , Volker Driesen , Juergen Specht
IPC分类号： G06F15/173
CPC分类号： H04L67/02 , G06F17/3089
摘要： Transporting of flexibility changes of customer content between tenants in a multi-tenant computing system can be performed by exporting customer content from a first tenant of the multi-tenant computing system, transporting the customer content exported from the first tenant to a second tenant of the multi-tenant computing system, importing the customer content into a staging area in the second tenant to enable a user associated with second tenant to access the customer content via the staging area based on a content extraction trigger, and activating selected customer content from the staging area in a productive component of the second tenant. The content extraction trigger can characterize an extraction of at least some of the customer content from the staging area. Related methods, systems, and articles of manufacture are also disclosed.
摘要翻译：可以通过从多租户计算系统的第一租户输出客户内容，将从第一租户输出的客户内容传送到第一租户的第二租户，来执行在多租户计算系统中的租户之间的客户内容的灵活性变化的传送多租户计算系统，将所述客户内容导入所述第二租户中的暂存区域，以使得与第二租户相关联的用户能够基于内容提取触发器经由所述登台区域访问所述客户内容，以及从所述分段激活所选择的客户内容第二租户生产部分的区域。内容提取触发器可以表征从分段区域提取至少一些客户内容。还公开了相关方法，系统和制品。

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