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1. 发明授权

US08689066B2 Integrated circuit test optimization using adaptive test pattern sampling algorithm 失效
标题翻译：使用自适应测试模式采样算法的集成电路测试优化
公开(公告)号：US08689066B2
公开(公告)日：2014-04-01
申请号：US13172179
申请日：2011-06-29
申请人： Matthew S. Grady , Mark C. Johnson , Bradley D. Pepper , Dean G. Percy , Joseph C. Pranys
发明人： Matthew S. Grady , Mark C. Johnson , Bradley D. Pepper , Dean G. Percy , Joseph C. Pranys
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/31835
摘要： A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.
摘要翻译：实现集成电路设备测试的方法包括使用全套测试模式来执行第一组芯片的基线测试，以及对于被识别为故障的芯片，确定全集中每个测试模式的得分。该分数表示测试图案相对于其他测试图案唯一地识别故障芯片的能力。在基线测试之后，使用由基线测试确定的具有最高平均分数的测试模式的一组减少的集合来执行第二组芯片的简化测试。在精简测试之后，使用完整的测试模式进行第三组芯片的全面测试，并更新每种模式的平均分数。进一步的测试在简化的测试和对另外一组芯片的完整测试之间进行了交替。

2. 发明申请

US20130007546A1 INTEGRATED CIRCUIT TEST OPTIMIZATION USING ADAPTIVE TEST PATTERN SAMPLING ALGORITHM 失效
标题翻译：使用自适应测试图形采样算法的集成电路测试优化
公开(公告)号：US20130007546A1
公开(公告)日：2013-01-03
申请号：US13172179
申请日：2011-06-29
申请人： Matthew S. Grady , Mark C. Johnson , Bradley D. Pepper , Dean G. Percy , Joseph C. Pranys
发明人： Matthew S. Grady , Mark C. Johnson , Bradley D. Pepper , Dean G. Percy , Joseph C. Pranys
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/263 , G01R31/31835
摘要： A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.
摘要翻译：实现集成电路设备测试的方法包括使用全套测试模式来执行第一组芯片的基线测试，以及对于被识别为故障的芯片，确定全集中每个测试模式的得分。该分数表示测试图案相对于其他测试图案唯一地识别故障芯片的能力。在基线测试之后，使用由基线测试确定的具有最高平均分数的测试模式的一组减少的集合来执行第二组芯片的简化测试。在精简测试之后，使用完整的测试模式进行第三组芯片的全面测试，并更新每种模式的平均分数。进一步的测试在简化的测试和对另外一组芯片的完整测试之间进行了交替。

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