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1. 发明授权

US08589320B2 Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks 有权
标题翻译：将二极管配置中的FET和可变电阻材料连接到神经元电路块的结的区域有效的神经元系统
公开(公告)号：US08589320B2
公开(公告)日：2013-11-19
申请号：US13548532
申请日：2012-07-13
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06E1/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
摘要翻译：神经元系统包括电连接到多个神经元电路块的多个突触块。多个突触块包括多个神经形态电路。每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入块。

2. 发明授权

US08311965B2 Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material 有权
标题翻译：使用场效应晶体管（FET）和可变电阻材料的区域效率的神经元电路
公开(公告)号：US08311965B2
公开(公告)日：2012-11-13
申请号：US12620624
申请日：2009-11-18
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06F17/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.
摘要翻译：神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点神经元电路。

3. 发明申请

US20120284217A1 AREA EFFICIENT NEUROMORPHIC SYSTEM 有权
标题翻译：区域有效的神经系统
公开(公告)号：US20120284217A1
公开(公告)日：2012-11-08
申请号：US13548532
申请日：2012-07-13
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06N3/04
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
摘要翻译：神经元系统包括电连接到多个神经元电路块的多个突触块。多个突触块包括多个神经形态电路。每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入块。

4. 发明申请

US20110119214A1 AREA EFFICIENT NEUROMORPHIC CIRCUITS 有权
标题翻译：区域有效的神经电路
公开(公告)号：US20110119214A1
公开(公告)日：2011-05-19
申请号：US12620624
申请日：2009-11-18
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06N3/063
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.
摘要翻译：神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点神经元电路。

5. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

6. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

7. 发明申请

US20100299297A1 SYSTEM FOR ELECTRONIC LEARNING SYNAPSE WITH SPIKE-TIMING DEPENDENT PLASTICITY USING PHASE CHANGE MEMORY 有权
标题翻译：使用相位变化记忆的具有SPIKE-TIMING相关塑性的电子学习系统
公开(公告)号：US20100299297A1
公开(公告)日：2010-11-25
申请号：US12470451
申请日：2009-05-21
申请人： Matthew Joseph Breitwisch , Roger W. Cheek , Chung Hon Lam , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Matthew Joseph Breitwisch , Roger W. Cheek , Chung Hon Lam , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06N3/063
CPC分类号： G06N3/049 , G06N3/0635 , G11C11/54 , G11C13/0004
摘要： A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.
摘要翻译：公开了一种用于在人造突触中产生尖峰依赖性可塑性的系统，方法和计算机程序产品。根据一个实施方案，用于在人造神经元中产生尖峰依赖性可塑性的方法包括当对第一神经元的总积分输入超过第一预定阈值时，在第一神经元中产生突触前尖峰事件。当到第二神经元的总积分输入超过第二预定阈值时，在第二神经元中产生突触后尖峰事件。在突触前尖峰事件之前，将第一脉冲施加到具有相变存储元件的突触的突触前突触节点。在突触后尖峰事件之后，将第二变化脉冲施加到突触的突触后结节，其中通过突触的电流是第一脉冲时的第二变化脉冲的状态的函数。

8. 发明授权

US07782646B2 High density content addressable memory using phase change devices 有权
标题翻译：使用相变装置的高密度内容寻址存储器
公开(公告)号：US07782646B2
公开(公告)日：2010-08-24
申请号：US12165530
申请日：2008-06-30
申请人： Chung Hon Lam , Bipin Rajendran
发明人： Chung Hon Lam , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/02 , G11C11/16 , G11C13/0004 , G11C15/04 , G11C15/046
摘要： A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices.
摘要翻译：一种在存储元件中存储存储字的内容可寻址存储器阵列。每个存储器元件将至少两个互补二进制位中的一个存储为至少两个互补电阻之一。每个存储器元件电耦合到访问设备。内容可寻址存储器阵列的一个方面是使用偏置电路来在搜索操作期间偏置访问设备。在搜索操作期间，接收包含位串的搜索词。每个访问设备被偏置到搜索词中相应搜索位的互补电阻值。如果存储在存储器元件中的位与由访问设备中的电阻表示的位互补，则指示搜索字和存储字之间的匹配。

9. 发明授权

US08350316B2 Phase change memory cells having vertical channel access transistor and memory plane 有权
标题翻译：具有垂直通道存取晶体管和存储器平面的相变存储单元
公开(公告)号：US08350316B2
公开(公告)日：2013-01-08
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L29/732
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

10. 发明授权

US07811879B2 Process for PCM integration with poly-emitter BJT as access device 有权
标题翻译：与多发射器BJT作为接入设备的PCM集成过程
公开(公告)号：US07811879B2
公开(公告)日：2010-10-12
申请号：US12121875
申请日：2008-05-16
申请人： Chung Hon Lam , Bipin Rajendran
发明人： Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L21/8249
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/101
摘要： Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.
摘要翻译：形成记忆体的技术。本发明的一个方面包括在衬底上形成FET栅极叠层和牺牲电池栅叠层。然后在FET栅极堆叠周围以及牺牲电池栅极堆叠周围形成间隔层。然后去除牺牲单元栅极堆叠，使得牺牲单元栅极堆叠周围的间隔层仍然完整。 BJT电池堆随后形成在形成和去除牺牲电池栅极堆叠的间隔层之间的空间中，BJT电池堆包括发射极层。然后形成发射极上方的相变层和相变层上方的电极。

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