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1. 发明专利

JP2003044284A Activation method for computer system and program for activation 审中-公开
标题翻译：计算机系统的激活方法和激活程序
公开(公告)号：JP2003044284A
公开(公告)日：2003-02-14
申请号：JP2001226875
申请日：2001-07-27
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MATSUZAKI YUTAKA , UEDA TOMIYASU , KATADA HISASHI , KOMINAMI SHINYA
IPC分类号： G06F1/00 , G06F9/445
摘要： PROBLEM TO BE SOLVED: To provide an activation method of a controller, capable of shortening activation time in the second or succeeding time and dissolving abnormality on a main memory, which is generated by the execution of software for control at the next activation.
SOLUTION: An operating system is loaded from a storage device onto the main memory and then the operating system is executed (steps 2 and 3). Then, the software for the control is loaded from the storage device onto the main memory (step 4) and data for the activation on the main memory immediately after the operating system is activated and the software for the control is loaded are preserved in the storage device as they are (step 5). Also, when the data for the activation are present in the storage device at activating the controller, that is at the activation of the second or succeeding time, the data for the activation are read onto the main memory (step 1 and 7).
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种控制器的激活方法，其能够缩短在第二次或之后的时间内的激活时间，并且通过执行下一次激活时的控制软件产生的主存储器上的异常。解决方案：将操作系统从存储设备加载到主存储器上，然后执行操作系统（步骤2和3）。然后，用于控制的软件从操作系统激活之后立即从存储设备加载到主存储器（步骤4）上并且在主存储器上激活的数据，并且用于控制的软件被加载到存储器中设备（步骤5）。此外，当激活控制器（即处于激活第二个或其后的时间）时激活的数据存在于存储装置中时，将激活的数据读入主存储器（步骤1和7）。

2. 发明专利

JP2003304099A Control method of production facility and operating system for performing the method 有权
标题翻译：用于执行方法的生产设施和操作系统的控制方法
公开(公告)号：JP2003304099A
公开(公告)日：2003-10-24
申请号：JP2002108080
申请日：2002-04-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SATO HIROSHI , KOMINAMI SHINYA , MIMURA NAOTO
IPC分类号： H05K13/04 , H05K13/08
摘要： PROBLEM TO BE SOLVED: To provide a control method and an operating system in which the risk of rewriting important data due to erroneous operation of the operating system of a production facility can be eliminated. SOLUTION: In the operating system for controlling the operation of the production facility comprising a personal computer 1, and an input device, e.g. a keyboard 2, for inputting information externally to the personal computer 1, an interface 4 connecting the input device with the personal computer 1 at the time of starting the personal computer 1 judges that the input device is under connection regardless of whether it is connected with the personal computer 1 or not so that the personal computer 1 can be actuated, and the input device can be inserted removably into the personal computer 1 without turning the power off even if the production facility is under operation. The input device may have an extension function capable of inserting an input device of arbitrary form removably. The input device is connected only when it is required thus eliminating erroneous operation of a worker. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供可以消除由于生产设施的操作系统的错误操作而重写重要数据的风险的控制方法和操作系统。解决方案：在用于控制包括个人计算机1的生产设备的操作的操作系统中，以及输入设备，例如，用于在个人计算机1外部输入信息的键盘2，在启动个人计算机1时连接输入设备与个人计算机1的接口4判断输入设备是否正在连接，而不管其是否与个人计算机1或者不使得个人计算机1能够被致动，并且即使生产设备正在运行，输入装置也可以可移除地插入到个人计算机1中而不关闭电源。输入装置可以具有能够插入任意形式的输入装置的扩展功能。输入设备仅在需要时连接，从而消除了工作人员的错误操作。版权所有（C）2004，JPO

3. 发明专利

JP2003271403A Control device and control device for mounting machine using the same 审中-公开
标题翻译：用于安装机器的控制装置和控制装置
公开(公告)号：JP2003271403A
公开(公告)日：2003-09-26
申请号：JP2002075282
申请日：2002-03-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UEDA TOMIYASU , MATSUZAKI YUTAKA , KATADA HISASHI , KOMINAMI SHINYA
IPC分类号： G06F9/46 , G06F9/48
摘要： PROBLEM TO BE SOLVED: To solve a problem of a conventional control device wherein the control device is difficult to be miniaturized and can't be mounted on equipment requiring miniaturization of the control device, since a system is constituted by using each different interruption bus signal to prevent a plurality of OSs from being overlapped and fixing each OS for every interruption level in each OS, when using the plurality of OSs. SOLUTION: This control device has an arithmetic device 1 having a plurality of operating systems, an interruption circuit 11 for inputting an interruption request signal into the arithmetic device 1 from the outside, and a resource control circuit 101. The resource control circuit 101 designates the assigning of the resource of the arithmetic device 1 to any operating system when an interruption request signal is given to the interruption circuit 11. After starting an interruption processing of the OS having the highest priority upon generation of an interruption by the resource control circuit 101, an interruption signal is used in common by the plurality of OSs by successively starting an OS interruption processing with the next highest priority. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题为了解决控制装置难以小型化并且不能安装在需要控制装置小型化的设备上的常规控制装置的问题，因为通过使用各种不同的方式构成系统中断总线信号，以防止多个OS重叠，并且在使用多个OS时在每个OS中为每个中断级固定每个OS。解决方案：该控制装置具有具有多个操作系统的运算装置1，用于从外部向运算装置1输入中断请求信号的中断电路11以及资源控制电路101.资源控制电路 101表示当向中断电路11给出中断请求信号时，将运算装置1的资源分配给任何操作系统。在通过资源控制产生中断时具有最高优先级的OS的中断处理电路101，通过连续地开始具有下一个最高优先级的OS中断处理，由多个OS共同使用中断信号。版权所有（C）2003，JPO

4. 发明专利

JPH02136756A OPTICAL SYSTEM ZERO-PHASE SENSOR SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH02136756A
公开(公告)日：1990-05-25
申请号：JP28874388
申请日：1988-11-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA
IPC分类号： G01R25/04 , G01R15/24
摘要： PURPOSE:To detect an output being proportional to only a modulation component by detecting a voltage and a current of power 3-phase AC by an optical fiber sensor, and controlling the light emission quantity so that a DC component of the detection light quantity always becomes constant. CONSTITUTION:Light quantity components from optical fiber sensors 1-3 are brought to O/E conversion by light receiving diodes 10-12, and inputted to a CPU 25 through light receiving amplifiers 13-15 and A/D converters 22-24. The CPU 25 calculates an average value of inputted signal data on a RAM 27 at every one period of a 3-phase AC, and compares it as a DC component of an input signal with a set value stored in advance in a ROM 28. When the average value is larger than the set value, the CPU 25 decreases a command value to D/A converters 29-31, decreases a current of LED amplifiers 4-6, decreases the light emission quantity of LEDs 7-9 and decreases the light quantity of the sensors 1-3. Therefore, the DC component of the input signal to the CPU 25 becomes constant, and a modulation component itself can be detected from the input signal.

5. 发明专利

JPH01136522A ZERO PHASE CURRENT SENSOR SIGNAL DISCRIMINATING CIRCUIT 失效
公开(公告)号：JPH01136522A
公开(公告)日：1989-05-29
申请号：JP29435487
申请日：1987-11-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA
IPC分类号： H02H3/32
摘要： PURPOSE:To make circuits to eliminate DC components for each phase unnecessary and to eliminate the effect of variations in characteristic of these elements by discriminating ground-fault accidents by time variation in an instantaneous sum of three phase current. CONSTITUTION:The current of each phase is detected by sensors 1-3, and is added by means of an adder 13 through amplifiers 4-6 and filters 7-9, the zero phase current is thereby detected. This signal is delayed through a delayer 14, and is compared with a signal not delaying by means of a comparator 15, when the difference is in excess of a threshold value set by a setting 16, the decision of ground-fault accidents is made. The decision is made by difference, so that it is not affected by DC components.

6. 发明专利

JPS63271604A SEQUENCE CONTROLLER 失效
公开(公告)号：JPS63271604A
公开(公告)日：1988-11-09
申请号：JP10669087
申请日：1987-04-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA
IPC分类号： G05B19/05 , G05B19/04
摘要： PURPOSE:To process a shift, etc., at a high speed by specifying a bus buffer which connects a data superposing circuit and a multibit data bus with an instruction code. CONSTITUTION:A general microcomputer 2 equipped with an 8-bit processor and a 1-bit processor 1 are combined together to constitute a sequencer controller. A 1-word 8-bit I/O memory 3 for storing an output state, the data superposing circuit 4 which substitutes bits outputted from the memory with the output of the 1-bit processor 1, and buffers B0-B7 are provided between the output part of the 1-bit processor 1 and the data bus 5 of the microcomputer 2, and a buffer encoder 8 is further provided. Then shift and rotation arithmetic instruction processes as to word and data processing instructions is performed only by specifying bus buffers B0-B7 which connect the superposing circuit 4 to the data bus 5 with instruction codes.

7. 发明专利

JPH06276204A LOOP-SHAPED I/O DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPH06276204A
公开(公告)日：1994-09-30
申请号：JP5853293
申请日：1993-03-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA , HARA YOSHIBUMI , SAKURAI TSUTOMU
IPC分类号： H04Q9/00 , H04L12/42
摘要： PURPOSE:To secure connection among the slave stations which process transmission signals of different address and data lengths in the same loop by providing such slave stations having the specific means included in the address coincidence detecting circuits to a master station containing a means which selectively transmit the address information. CONSTITUTION:A master station 5 is provided with a means which selectively transmits the address information that undergone the adjacent inversion or the adjacent non-inversion. A slave station 3 contains an adjacent inversion collating means included in an address coincidence detecting circuit, and a slave station 15 contains an adjacent non-inversion collating means included in an address coincidence detecting circuit. In such a constitution, the address information is used as an adjacent inversion signal and an adjacent non-inversion signal for transmission of the transmission signals of the ordinary address and data lengths and the transmission signals of different address and data lengths respectively. As a result, the transmission signals of different address and data lengths pass through the station 3 and undergo the input/output of data through the station 15 respectively.

8. 发明专利

JPH06241896A LIGHT-AMOUNT DETECTING CIRCUIT 失效
公开(公告)号：JPH06241896A
公开(公告)日：1994-09-02
申请号：JP2698093
申请日：1993-02-16
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA , KAWANO HAJIME , IHARA AKIRA
IPC分类号： G01J1/44 , H03K17/78 , H04B10/079 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/04 , H04B10/06
摘要： PURPOSE:To perform the judgment of the proper amount of light normally even if the lengths of transmitted data and transmitting cycles are different. CONSTITUTION:A photoelectric converter 2 converts an optical pulse signal into an electric pulse signal. A diode 4 makes the pulse signal flow in one direction. The pulse signal is charged into a capacitor 5. An A/D converter 6 performs the A/D conversion for the charged voltage. A counter 7 counts the pulse signals. A CPU 8 operates the data from the A/D converter 6 and the counter 7. These parts are provided. The data from the A/D converter 6 and the data from the counter are operated, and the amount of the light per pulse is detected.

9. 发明专利

JPH05102984A LOOP SHAPE I/O DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPH05102984A
公开(公告)日：1993-04-23
申请号：JP26179291
申请日：1991-10-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA
IPC分类号： H04L12/42
摘要： PURPOSE:To perform data transmission without re-registering information for the address and specification data of every slave station when they are registered in advance or the change of the address and the change and deletion of specification are performed by automatically recognizing the connecting state of the slave station. CONSTITUTION:This device is composed of a command coincidence detection memory circuit 14 which comprises a transmission signal of synchronous information, address information, and data information and command information to issue an instruction so as to check the information with respect to the slave station, and also, generates a signal in accordance with the command information, and a byte change-over switch circuit 11 which substitues input data 1 for the information with respect to the slave station by the signal outputted from the command coincidence detection memory circuit 14. Thereby, the purpose can be attained since each slave station transmits respective address and the information with respect to the connecting state of the slave station to a master station.

10. 发明专利

JPH056206A TEACHING PLAYBACK SEQUENCER 失效
公开(公告)号：JPH056206A
公开(公告)日：1993-01-14
申请号：JP15661591
申请日：1991-06-27
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOMINAMI SHINYA
IPC分类号： G05B19/05 , G05B19/048
摘要： PURPOSE:To provide the teaching playback sequencer which can confirm the equipment of a teaching system and exactly and efficiently execute program registration depending on teaching playback by turning on a confirmation switch even when there are a lot of equipments such as actuators or the like connected to an output port. CONSTITUTION:This device is equipped with a confirmation switch 1, means to detect time for this confirmation switch 1 to be turned on, pulse generating means to generate a pulse signal successively prolonging the pulse width together with the passage of the time while the confirmation switch 1 is turned on, means to output the pulse signal to an output port 4, address switch 6 to switch the address of the output port, teaching switch 9 to apply teaching timing and program memory 8 to register taught I/O states in the order of steps.

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