专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070118784A1 SELF TEST CIRCUIT FOR A SEMICONDUCTOR INTERGRATED CIRCUIT 有权
标题翻译：用于半导体集成电路的自检测电路
公开(公告)号：US20070118784A1
公开(公告)日：2007-05-24
申请号：US11555524
申请日：2006-11-01
申请人： Massahiro Fusumada , Hitoshi Saitoh , Shinji Togashi , Akira Yano
发明人： Massahiro Fusumada , Hitoshi Saitoh , Shinji Togashi , Akira Yano
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3187
摘要： A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.
摘要翻译：一种半导体集成电路，可以自我测试LVDS中时钟和数据信号的偏移余量。时钟信号CKB 1与检查时钟信号A 1同步地保持在触发器电路105中。检查模式信号PAT_A与检查时钟信号A 2同步地保持在触发器电路104中。当检查时钟信号CKA_IN和数据信号DA_IN的偏斜边缘时，输入触发器电路105的检查信号TCKA而不是时钟信号CKA_IN，并且输入触发器电路104的检查信号TDA而不是时钟信号 DA_IN。定时控制电路109独立地控制时钟信号CKB 7与检查定时信号A 1之间的时序关系以及时钟信号CKB 7与检查定时信号A2之间的时序关系。

2. 发明授权

US07730374B2 Self test circuit for a semiconductor intergrated circuit 有权
标题翻译：半导体集成电路自检电路
公开(公告)号：US07730374B2
公开(公告)日：2010-06-01
申请号：US11555524
申请日：2006-11-01
申请人： Massahiro Fusumada , Hitoshi Saitoh , Shinji Togashi , Akira Yano
发明人： Massahiro Fusumada , Hitoshi Saitoh , Shinji Togashi , Akira Yano
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3187
摘要： A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2. When the skew margin of clock signal CKA_IN and data signal DA_IN are checked, the checking signal TCKA of flip-flop circuit 105 is input instead of clock signal CKA_IN, and the checking signal TDA of flip-flop circuit 104 is input instead of clock signal DA_IN. The timing relationship between clock signal CKB7 and checking timing signal A1 and the timing relationship between clock signal CKB7 and checking timing signal A2 are controlled independently by timing control circuit 109.
摘要翻译：一种半导体集成电路，可以自我测试LVDS中时钟和数据信号的偏移余量。时钟信号CKB1与检查时钟信号A1同步地保持在触发器电路105中。检查模式信号PAT_A与检查时钟信号A2同步地保持在触发器电路104中。当检查时钟信号CKA_IN和数据信号DA_IN的偏斜边缘时，输入触发器电路105的检查信号TCKA而不是时钟信号CKA_IN，并且输入触发器电路104的检查信号TDA而不是时钟信号 DA_IN。定时控制电路109独立地控制时钟信号CKB7与检查定时信号A1之间的时序关系以及时钟信号CKB7与检查定时信号A2之间的定时关系。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式