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1. 发明授权

US5245613A Digital signal time-division multiplex apparatus 失效
标题翻译：数字信号时分复用装置
公开(公告)号：US5245613A
公开(公告)日：1993-09-14
申请号：US702402
申请日：1991-05-20
申请人： Masayuki Takami , Takehiko Atsumi
发明人： Masayuki Takami , Takehiko Atsumi
IPC分类号： H05K7/14 , H04J3/06
CPC分类号： H04J3/0685
摘要： In a digital signal time-division multiplex apparatus according to the present invention, digital signals transmitted through a plurality of channels are converted into low-order section frame signals in response to sync signals by low-order section frame processing boards provided for their respective channels. The low-order section frame processing boards are arranged in parallel on a mother board at regular intervals. The low-order section frame signals processed by the low-order section frame processing boards are supplied to a high-order section frame processing board and sequentially selected within one frame, thereby generating time-division multiplex signals. The sync signals are generated by a sync signal generating board and transmitted to a sync signal transmitting line formed on the mother board. The sync signal transmitting line is formed so as to transmit the sync signals in a direction in which the low-order section frame processing boards are arranged. The sync signals are supplied to the low-order section frame processing boards through the sync signal transmitting line in a bus line system. The low-order section frame signals generated from the low-order section frame processing boards are transmitted to a plurality of low-order section frame signal transmitting lines formed in the direction in which the sync signals are transmitted, and supplied to the high-order section frame processing board through the low-order section frame signal transmission lines.
摘要翻译：在根据本发明的数字信号时分多路复用装置中，通过多个信道发送的数字信号通过为各自信道提供的低阶部分帧处理板响应于同步信号而被转换为低阶部分帧信号。低阶部分框架处理板以规则的间隔平行布置在母板上。由低阶部分帧处理板处理的低阶部分帧信号被提供给高阶部分帧处理板，并在一帧内顺序选择，从而产生时分复用信号。同步信号由同步信号发生板产生并发送到形成在母板上的同步信号传输线。形成同步信号传输线，以便在布置低阶部分帧处理板的方向上发送同步信号。同步信号通过总线系统中的同步信号发送线路提供给低阶部分帧处理板。从低阶部分帧处理板产生的低阶部分帧信号被发送到在发送同步信号的方向上形成的多个低阶部分帧信号传输线，并被提供给高阶部分帧信号段框处理板通过低阶段帧信号传输线。

2. 发明授权

US4899339A Digital multiplexer 失效
标题翻译：数字多路复用器
公开(公告)号：US4899339A
公开(公告)日：1990-02-06
申请号：US254847
申请日：1988-10-07
申请人： Taro Shibagaki , Takehiko Atsumi , Hiroyuki Ibe , Sadao Tanikoshi
发明人： Taro Shibagaki , Takehiko Atsumi , Hiroyuki Ibe , Sadao Tanikoshi
IPC分类号： H04J3/07
CPC分类号： H04J3/073
摘要： N framing units block N-channel input digital signals, respectively, to provide blocked signals. The framing units respond to a common block synchronization signal from a multiplexing unit to provide the blocked signals in a time relation suitable for multiplexing. The multiplexing unit multiplexes the blocked signals from the framing units to provide a multiplexed signal (higher-order group signal).

3. 发明授权

US5276439A Digital signal exchange equipment 失效
标题翻译：数字信号交换设备
公开(公告)号：US5276439A
公开(公告)日：1994-01-04
申请号：US969519
申请日：1992-10-30
申请人： Takehiko Atsumi , Hiroyuki Ibe , Taro Shibagaki , Takeshi Ozeki
发明人： Takehiko Atsumi , Hiroyuki Ibe , Taro Shibagaki , Takeshi Ozeki
IPC分类号： H04Q11/04 , H04B3/38
CPC分类号： H04Q11/04
摘要： A digital signal exchange equipment is disclosed which is constructed of a combination of selector modules each constituted by a plurality of gate arrays as a parallel unit in a column direction. The respective gate array comprises a first gate for selecting one line from an n number of first input lines and connecting it to an output line, a second gate for selecting one line from an output line of the first gate and one second input line and connecting it to the second gate and a flip-flop for wave-shaping an output of the second gate and, at the same time, taking synchronization among the respective gate array. The selector module as set forth above is constructed of a semiconductor circuit device. When, in particular, a plurality of selector modules are combined together, they are arranged as a k-column/l-row array in which input bus lines are each connected to each common row and an n number of output lines are connected for each row to an n number of second input lines of the next-row selector module.
摘要翻译：公开了一种数字信号交换设备，其由选择器模块的组合构成，每个选择器模块由沿列方向的并联单元的多个门阵列构成。相应的门阵列包括用于从n个第一输入线选择一条线并将其连接到输出线的第一栅极，用于从第一栅极的输出线选择一条线的第二栅极和一个第二输入线和连接它到第二栅极和用于对第二栅极的输出进行波形整形的触发器，并且同时在各个栅极阵列之间取得同步。如上所述的选择器模块由半导体电路器件构成。特别地，将多个选择器模块组合在一起时，它们被布置为k列/ l行阵列，其中输入总线各自连接到每个公共行，并且每个连接n个输出线行到下一行选择器模块的n个第二输入行。

4. 发明授权

US5140618A Frame synchronization circuit 失效
标题翻译：帧同步电路
公开(公告)号：US5140618A
公开(公告)日：1992-08-18
申请号：US651013
申请日：1991-02-05
申请人： Osamu Kinoshita , Takako Mori , Hideki Ishibashi , Hiroyuki Ibe , Takehiko Atsumi
发明人： Osamu Kinoshita , Takako Mori , Hideki Ishibashi , Hiroyuki Ibe , Takehiko Atsumi
IPC分类号： H04J3/00 , H04J3/06 , H04L7/08
CPC分类号： H04J3/0608
摘要： In a frame synchronization circuit, a serial data signal, which includes a frame synchronization code constituted by an M number of bits in one frame, is converted by a serial/parallel converting circuit to a parallel data signal of a 2M-1 number of bits. An M number of pattern detectors of a first synchronization detecting circuit detect the code pattern of the first block of the frame synchronization code from the parallel data signal. A selection signal generating circuit holds outputs of the pattern detectors, and outputs them as a selection signal designating the bit position allotted to the pattern detector which detects the synchronization code pattern. An output of the serial/parallel converting circuit is delayed by a time required for the above-mentioned processing, and supplied to a selector, which selectively outputs an M-bit data signal corresponding to the bit position designated by the selection signal.
摘要翻译：在帧同步电路中，包括由一帧中的M个位组成的帧同步码的串行数据信号由串/并转换电路转换为2M-1位的并行数据信号。 M个第一同步检测电路的模式检测器从并行数据信号检测帧同步码的第一块的码模式。选择信号发生电路保持图案检测器的输出，并输出它们作为指定分配给检测同步码模式的图案检测器的位位置的选择信号。串行/并行转换电路的输出被延迟上述处理所需的时间，并提供给选择器，选择器输出与由选择信号指定的位位置对应的M位数据信号。

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