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1. 发明申请

US20080007285A1 Handler and method of testing semiconductor device by means of the handler 审中-公开
标题翻译：处理程序和通过处理程序测试半导体器件的方法
公开(公告)号：US20080007285A1
公开(公告)日：2008-01-10
申请号：US11822219
申请日：2007-07-03
申请人： Masayuki Nakase , Kouji Akahori , Tomohiko Kanemitsu , Yasuhiro Kamatani
发明人： Masayuki Nakase , Kouji Akahori , Tomohiko Kanemitsu , Yasuhiro Kamatani
IPC分类号： G01R31/26
CPC分类号： G01R31/2893
摘要： An object of the present invention is to provide a handler and a testing method thereof which enable efficient measurements on a plurality of semiconductor devices. An arm control unit 106 controls, for each of contact arms 101a and 101b, the timing of control for performing contact control for bringing semiconductor devices 103a and 103b to be tested to one of a contact state and a non-contact state with test boards 108a and 108b connected to semiconductor testers 109a and 109b. The plurality of semiconductor devices are simultaneously measured using the handler 107, so that when a “defective item” is found on a specific measurement part, only the defective item on the measurement part can be replaced with another untested item and thus tests can be efficiently conducted.
摘要翻译：本发明的目的是提供一种能够在多个半导体器件上进行高效测量的处理器及其测试方法。臂控制单元106对于接触臂101a和101b中的每一个控制用于进行接触控制的控制的定时，以使要测试的半导体器件103a和103b成为接触状态和非接触状态之一测试板108a和108b连接到半导体测试器109a和109b。使用处理器107同时测量多个半导体器件，使得当在特定测量部分上发现“缺陷项目”时，只有测量部分上的缺陷项目可以被替换为另外未测试的项目，因此可以有效地进行测试进行。

2. 发明申请

US20060200714A1 Test equipment for semiconductor 审中-公开
标题翻译：半导体测试设备
公开(公告)号：US20060200714A1
公开(公告)日：2006-09-07
申请号：US11363948
申请日：2006-03-01
申请人： Satoru Kamano , Tomohiko Kanemitsu
发明人： Satoru Kamano , Tomohiko Kanemitsu
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C2029/5602
摘要： A test equipment for semiconductor according to the present invention comprises a equipment main body and a memory cell provided in an outside of the equipment main body, wherein the equipment main body comprises a configurable device capable of making a hardware construction in a programmable manner and an interface for connecting the configurable device to the outside of the equipment main body in order to configure the configurable device, and the memory cell, in which a regulation program for the hardware construction for regulating the hardware construction of the configurable device is written, is connected in freely attached or removed way to the configurable device via the interface.
摘要翻译：根据本发明的用于半导体的测试设备包括设备主体和设置在设备主体外部的存储单元，其中设备主体包括能够以可编程方式制造硬件结构的可配置设备，以及用于将可配置设备连接到设备主体外部以便配置可配置设备的接口，以及其中写入用于调节可配置设备的硬件结构的硬件结构的调节程序的存储单元被连接通过接口自由连接或移除到可配置设备。

3. 发明申请

US20050258856A1 High-speed interface circuit test module, module under high-speed interface circuit test, and high-speed interface circuit test method 审中-公开
标题翻译：高速接口电路测试模块，模块高速接口电路测试，高速接口电路测试方法
公开(公告)号：US20050258856A1
公开(公告)日：2005-11-24
申请号：US11133290
申请日：2005-05-20
申请人： Satoshi Kishimoto , Tomohiko Kanemitsu , Michio Maekawa
发明人： Satoshi Kishimoto , Tomohiko Kanemitsu , Michio Maekawa
IPC分类号： G01R31/28 , G01R31/26 , G01R31/30 , G01R31/317 , G01R31/319 , G06F13/00 , H04L12/26
CPC分类号： G01R31/31905 , G01R31/3016 , G01R31/31712 , G01R31/31926 , H04L43/50
摘要： In the shipment test of an LSI provided with a high-speed interface circuit, both cost reduction and a high test guarantee level are realized. The following are provided: a high-speed interface circuit that is mounted on a load board interfacing with an LSI tester, is provided with a circuit converting the signal speed, and is capable of changing the transmission and reception characteristics; a controller that controls the transmission and reception characteristics of the high-speed interface circuit; a clock generator that generates the clock supplied to the high-speed interface circuit; a first connector provided specifically for the high-speed interface, connected to the high-speed interface circuit and provided with a signal port for performing high-speed signal communication with a circuit under test; and a second connector connected to the high-speed interface circuit and the LSI tester and provided with a signal port and a power port for performing low-speed signal communication with the high-speed interface circuit.
摘要翻译：在具有高速接口电路的LSI的出货测试中，实现了成本降低和高测试保证水平。提供以下内容：安装在与LSI测试器接口的负载板上的高速接口电路设置有转换信号速度的电路，并且能够改变发送和接收特性; 控制器，其控制高速接口电路的发送和接收特性; 产生提供给高速接口电路的时钟的时钟发生器; 专为高速接口而设计的第一连接器，连接到高速接口电路并且设置有用于与被测电路进行高速信号通信的信号端口; 以及连接到高速接口电路和LSI测试器的第二连接器，并且设置有用于与高速接口电路进行低速信号通信的信号端口和电源端口。

4. 发明申请

US20090243640A1 CONDUCTIVE CONTACT PIN AND SEMICONDUCTOR TESTING EQUIPMENT 审中-公开
标题翻译：导电接触针和半导体测试设备
公开(公告)号：US20090243640A1
公开(公告)日：2009-10-01
申请号：US12409965
申请日：2009-03-24
申请人： Nobuhiro Katsuma , Tomohiko Kanemitsu , Takashi Ogawa
发明人： Nobuhiro Katsuma , Tomohiko Kanemitsu , Takashi Ogawa
IPC分类号： G01R31/02
CPC分类号： G01R1/06722 , G01R1/06738 , G01R1/07314 , G01R31/2886
摘要： In a conductive contact pin brought into contact with the external electrode of a semiconductor device to conduct a test on the electrical characteristics of the semiconductor device, an upper plunger 13 which is a contact pin coming in and out of a cylindrical body is made up of a base b which is in sliding contact with the cylindrical body and is not in contact with the external electrode and an end a which comes into contact with the external electrode. The base b has at least a surface layer made of a precious metal, and the end a has at least a surface layer made of one of a different metal from the base b and a metal alloy.
摘要翻译：在与半导体器件的外部电极接触的导电接触针中，对半导体器件的电气特性进行测试，作为进入和离开圆筒体的接触针的上部柱塞13由以下部件组成：与圆柱体滑动接触并且不与外部电极接触的基底b和与外部电极接触的端部a。基体b至少具有由贵金属构成的表面层，端部a至少具有由与基体b不同的金属之一构成的表面层和金属合金。

5. 发明授权

US07148676B2 Ancillary equipment for testing semiconductor integrated circuit 有权
标题翻译：半导体集成电路测试辅助设备
公开(公告)号：US07148676B2
公开(公告)日：2006-12-12
申请号：US10726891
申请日：2003-12-04
申请人： Satoru Kamano , Tomohiko Kanemitsu
发明人： Satoru Kamano , Tomohiko Kanemitsu
IPC分类号： G01R31/28
CPC分类号： G01R31/31907
摘要： An ancillary equipment is provided for testing a semiconductor integrated circuit, by which a plurality of BOST boards serving as measuring units can be set near a device to be measured and tests can be conducted with high accuracy on a number of circuits embedded on a semiconductor integrated circuit such as a system LSI. To achieve an object of performing a go/no go test or a functional/performance characterization in the manufacturing process of the semiconductor integrated circuit, the ancillary equipment includes: a device measuring unit having a measuring section for exchanging a signal with a device or a semiconductor integrated circuit, and an analyzing section for analyzing information from the measuring section using a programmable device; and a control/communication card constituted of a board different from that of the device measuring unit and connected to the device measuring unit to control it, and being capable of performing communication with a general-purpose computer.
摘要翻译：提供了用于测试半导体集成电路的辅助设备，通过该半导体集成电路可以将多个用作测量单元的BOST板设置在要测量的设备附近，并且可以在嵌入在半导体集成电路上的多个电路上以高精度进行测试电路如系统LSI。为了实现在半导体集成电路的制造过程中执行去/禁止测试或功能/性能表征的目的，辅助设备包括：设备测量单元，具有用于与设备或设备交换信号的测量部分半导体集成电路和用于使用可编程器件分析来自测量部分的信息的分析部分; 以及由与设备测量单元不同的板构成的控制/通信卡，并连接到设备测量单元以进行控制，并且能够与通用计算机进行通信。

6. 发明申请

US20080094096A1 Semiconductor testing equipment and semiconductor testing method 审中-公开
标题翻译：半导体测试设备和半导体测试方法
公开(公告)号：US20080094096A1
公开(公告)日：2008-04-24
申请号：US11878466
申请日：2007-07-24
申请人： Satoshi Kishimoto , Tomohiko Kanemitsu
发明人： Satoshi Kishimoto , Tomohiko Kanemitsu
IPC分类号： G01R31/26
CPC分类号： G01R31/2894 , G01R31/31721
摘要： In testing a large number of semiconductor devices, semiconductor testing equipment of the present invention is provided with combination determining unit 105 that determines the combination of semiconductor devices to be simultaneously tested among semiconductor devices to be tested, on the basis of one of determination results or measured values in separate testing or manufacturing implemented before and stored in a memory 99, and past determination results or measured values stored in the memory 99 in the present testing.
摘要翻译：在测试大量半导体器件时，本发明的半导体测试设备提供有组合确定单元105，组合确定单元105基于确定结果之一确定待测试的半导体器件之间要同时测试的半导体器件的组合，在存储器99之前实施并存储在存储器99中的单独的测试或制造中的测量值以及在本测试中存储在存储器99中的过去的确定结果或测量值。

7. 发明授权

US07251761B2 Assembly for LSI test and method for the test 有权
标题翻译：用于LSI测试的组装和测试方法
公开(公告)号：US07251761B2
公开(公告)日：2007-07-31
申请号：US10637663
申请日：2003-08-11
申请人： Wataru Itoh , Tomohiko Kanemitsu , Takeru Yamashita , Akihiko Watanabe
发明人： Wataru Itoh , Tomohiko Kanemitsu , Takeru Yamashita , Akihiko Watanabe
IPC分类号： G01R31/28
CPC分类号： G01R31/31921 , G01R31/3193 , G01R31/31935
摘要： An assembly for an LSI test supplies a test signal output from an LSI tester to a target LSI to be tested and outputs, to the LSI tester, a test result signal generated by processing of the target LSI performed in accordance with the test signal. The assembly for an LSI test includes: a peripheral circuit coupled to the target LSI and allowing the target LSI to operate in the same manner as in the application environment; and a printed circuit board on which the peripheral circuit is mounted.
摘要翻译：用于LSI测试的组件将从LSI测试器输出的测试信号提供给要测试的目标LSI，并向LSI测试器输出根据测试信号执行的目标LSI的处理产生的测试结果信号。用于LSI测试的组件包括：连接到目标LSI并允许目标LSI以与应用环境相同的方式操作的外围电路; 以及安装有外围电路的印刷电路板。

8. 发明授权

US06393564B1 Decrypting device 失效
标题翻译：解密设备
公开(公告)号：US06393564B1
公开(公告)日：2002-05-21
申请号：US09163257
申请日：1998-09-29
申请人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
发明人： Tomohiko Kanemitsu , Naoya Tokunaga , Kenta Sokawa , Hiroshi Miyaguchi
IPC分类号： G06F124
CPC分类号： H04L9/0877 , H04L2209/08
摘要： The decrypting device of this invention includes: a decrypting key generation circuit for generating a decrypting key based on first decrypting key information and second decrypting key information; and a decrypting circuit for decrypting encrypted information using the decrypting key, wherein the first decrypting key information is input from outside the decrypting device, and the second decrypting key information is stored inside the decrypting device.
摘要翻译：本发明的解密装置包括：解密密钥生成电路，用于基于第一解密密钥信息和第二解密密钥信息生成解密密钥; 以及解密电路，用于使用解密密钥对加密信息进行解密，其中，从解密装置外部输入第一解密密钥信息，第二解密密钥信息存储在解密装置内。

9. 发明授权

US07733112B2 Semiconductor testing circuit and semiconductor testing method 失效
标题翻译：半导体测试电路和半导体测试方法
公开(公告)号：US07733112B2
公开(公告)日：2010-06-08
申请号：US12173860
申请日：2008-07-16
申请人： Satoshi Kishimoto , Tomohiko Kanemitsu
发明人： Satoshi Kishimoto , Tomohiko Kanemitsu
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28
CPC分类号： G01R31/31725
摘要： A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.
摘要翻译：本发明的半导体测试电路包括连接到不被测试的终端的信号线和待测半导体器件的多个终端; 开关电路，用于控制信号线与要测试的端子之间的电连接/断开; 和连接到信号线一端的电阻。利用这种配置，在对输入信号的AC特性进行测试时，由LSI测试仪产生的测试信号可以通过不经测试的终端和通过接通开关电路的信号线输入到要测试的终端。

10. 发明申请

US20090021279A1 SEMICONDUCTOR TESTING CIRCUIT AND SEMICONDUCTOR TESTING METHOD 失效
标题翻译：半导体测试电路和半导体测试方法
公开(公告)号：US20090021279A1
公开(公告)日：2009-01-22
申请号：US12173860
申请日：2008-07-16
申请人： Satoshi Kishimoto , Tomohiko Kanemitsu
发明人： Satoshi Kishimoto , Tomohiko Kanemitsu
IPC分类号： G01R31/26
CPC分类号： G01R31/31725
摘要： A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.
摘要翻译：本发明的半导体测试电路包括连接到不被测试的终端的信号线和待测半导体器件的多个终端; 开关电路，用于控制信号线与要测试的端子之间的电连接/断开; 和连接到信号线一端的电阻。利用这种配置，在对输入信号的AC特性进行测试时，由LSI测试仪产生的测试信号可以通过不经测试的终端和通过接通开关电路的信号线输入到要测试的终端。

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