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1. 发明授权

US5796647A Inner product calculation device 失效
标题翻译：内产品计算装置
公开(公告)号：US5796647A
公开(公告)日：1998-08-18
申请号：US599746
申请日：1996-02-12
申请人： Kunihiko Iizuka , Mitsuhiko Fujio , Hirofumi Matsui , Masayuki Miyamoto
发明人： Kunihiko Iizuka , Mitsuhiko Fujio , Hirofumi Matsui , Masayuki Miyamoto
IPC分类号： G06G7/14 , G06G7/16 , G06J1/00 , G06G7/00
CPC分类号： G06J1/005 , G06G7/14 , G06G7/16
摘要： An inner product calculation device for calculating an inner product of a coefficient vector including at least one first element with a positive sign and at least one second element with a negative sign and an input vector including elements corresponding to a plurality of input voltages. The device includes: an amplifier having an input terminal and an output terminal; a first capacitor corresponding to the first element and having a capacitance in proportion to a value of the first element; a second capacitor corresponding to the second element, and having a capacitance in proportion to an absolute value of the second element; a third capacitor connected to one end of the first capacitor, one end of the second capacitor, and the input terminal of the amplifier; a voltage source applying, during a first period a corresponding one of the input voltages to the first capacitor and a reference voltage to the second capacitor and the third capacitor; and applying, during a second period following the first period, the reference voltage to the first capacitor, a corresponding one of the plurality of input voltages to the second capacitor, and an output voltage output from the output terminal of the amplifier to the third capacitor; and a switch for short-circuiting the input terminal of the amplifier and the output terminal of the amplifier during a third period.
摘要翻译：一种内积计算装置，用于计算包括具有正符号的至少一个第一元素和至少一个具有负号的第二元素的系数向量和包括与多个输入电压对应的元素的输入向量的内积。该装置包括：具有输入端和输出端的放大器; 对应于所述第一元件的第一电容器，并且具有与所述第一元件的值成比例的电容; 对应于第二元件的第二电容器，并且具有与第二元件的绝对值成比例的电容; 连接到第一电容器一端的第三电容器，第二电容器的一端和放大器的输入端; 电压源，在第一时段期间将与所述第一电容器的输入电压相对应的一个施加到所述第二电容器和所述第三电容器的基准电压; 以及在所述第一周期之后的第二时段期间将参考电压施加到所述第一电容器，将所述多个输入电压中的相应一个施加到所述第二电容器，以及从所述放大器的输出端子输出到所述第三电容器的输出电压 ; 以及用于在第三周期期间使放大器的输入端子和放大器的输出端子短路的开关。

2. 发明授权

US5845016A Image compressing apparatus 失效
标题翻译：图像压缩装置
公开(公告)号：US5845016A
公开(公告)日：1998-12-01
申请号：US673720
申请日：1996-06-27
申请人： Hirofumi Matsui , Kunihiko Iizuka , Masayuki Miyamoto , Mitsuhiko Fujio
发明人： Hirofumi Matsui , Kunihiko Iizuka , Masayuki Miyamoto , Mitsuhiko Fujio
IPC分类号： H04N19/00 , G06T9/00 , H03M7/30 , H04N1/41 , H04N19/124 , H04N19/154 , H04N19/176 , H04N19/196 , H04N19/85 , H04N19/94 , G06K9/38
CPC分类号： H04N19/94 , G06T9/008 , H03M7/3082
摘要： An image compressing apparatus employs a mean-separated normalized vector quantization method according to which, with respect to vector components corresponding to input images inputted from image sensors via a plurality of lines, encodes and outputs a scalar-quantized code of a mean value, a scalar-quantized code of a maximum scalar product value with each code word in a code book, and an index of one of the code words which yields a maximum scalar product value. In this image compressing apparatus, when the maximum scalar product value is less than a predetermined threshold value, in accordance with judgement by a comparator circuit, an output selecting circuit stops outputting the codes of the maximum scalar product value and of the index, and outputs only the code of the mean value. Therefore, when the image is uniform with pixels varying little in their luminance levels in compression processing unit blocks, code data to be outputted are restricted so that only data of the mean value are outputted. Consequently, it is possible to restrain degradation of the image and to considerably reduce data amount.
摘要翻译：图像压缩装置采用平均分离的归一化矢量量化方法，根据该量化方法，对于与通过多行从图像传感器输入的输入图像相对应的矢量分量，编码并输出平均值的标量化码，具有代码本中的每个代码字的最大标量积值的标量化代码，以及产生最大标量乘积值的代码字之一的索引。在该图像压缩装置中，当最大标量乘积值小于预定阈值时，根据比较器电路的判断，输出选择电路停止输出最大标量乘积值和索引的代码，并输出只有代码的平均值。因此，当在压缩处理单元块中图像的亮度级别变化很小的图像均匀时，要输出的代码数据被限制，从而仅输出平均值的数据。因此，可以抑制图像的劣化并且显着地减少数据量。

3. 发明授权

US5818267A Input detector 失效
标题翻译：输入检测器
公开(公告)号：US5818267A
公开(公告)日：1998-10-06
申请号：US808565
申请日：1997-02-28
申请人： Mitsuhiko Fujio , Masayuki Miyamoto , Kunihiko Iizuka , Hirofumi Matsui
发明人： Mitsuhiko Fujio , Masayuki Miyamoto , Kunihiko Iizuka , Hirofumi Matsui
IPC分类号： G01R19/165 , G01R19/00 , H03L5/00
CPC分类号： G01R19/0038
摘要： In respective comparators, a plurality of input voltages are compared with a comparison voltage that has been swept, and only the binary output of a D flipflop corresponding to the comparator that has exceeded the comparison voltage earliest is allowed to have "1", while the outputs corresponding to the rest of the comparators have "0". Therefore, it is possible to detect a maximum output by using the comparators of a normal CMOS construction and a binary-change detection means circuit constituted by logical circuits. Compared with the application of floating-gate MOS, this arrangement makes it possible to reduce costs, and also to easily carry out offset-voltage compensation for each comparator by using switched capacitors. As a result, in a maximum input detector which detects a maximum input from analog inputs through multiple channels by carrying out analog operations, it is possible to reduce costs, and also to improve detection precision.
摘要翻译：在各个比较器中，将多个输入电压与已经被扫描的比较电压进行比较，并且只有比较器对应于比较器的D触发器的二进制输出已经超过比较电压最早才被允许为“1”，而对应于其余比较器的输出具有“0”。因此，可以通过使用通常的CMOS结构的比较器和由逻辑电路构成的二进制变化检测装置电路来检测最大输出。与浮栅MOS的应用相比，这种布置使得可以降低成本，并且还可以通过使用开关电容器容易地对每个比较器执行偏移电压补偿。结果，在通过执行模拟操作来检测通过多个通道的模拟输入的最大输入的最大输入检测器中，可以降低成本，并且还可以提高检测精度。

4. 发明授权

US5878171A Encoding apparatus 失效
标题翻译：编码装置
公开(公告)号：US5878171A
公开(公告)日：1999-03-02
申请号：US671418
申请日：1996-06-27
申请人： Masayuki Miyamoto , Kunihiko Iizuka , Hirofumi Matsui , Mitsuhiko Fujio
发明人： Masayuki Miyamoto , Kunihiko Iizuka , Hirofumi Matsui , Mitsuhiko Fujio
IPC分类号： H04N19/00 , G06T9/00 , G10L19/038 , G10L19/16 , H03M1/12 , H03M7/30 , H04N1/41 , H04N19/42 , H04N19/85 , H04N19/94 , G06K9/38
CPC分类号： G06T9/008 , H03M7/3082 , H04N19/94
摘要： An encoding apparatus uses a vector quantization encoding method for encoding indexes of codewords, which supply a scalar quantized code of a maximum scalar product value of each code word in a code book, and its maximum scalar product value to a vector component of an input image inputted from an image sensor, so as to output the encoded indexes. A scalar product value calculating circuit in the encoding apparatus has scalar product value calculating sections, which are composed of an analog circuit having a code component capacitor corresponding to each code component, a differential amplifier and a feedback capacitor, corresponding to each codeword, and the scalar product values of the input vectors are calculated in parallel by the scalar product value calculating sections. In such a manner, when the analog calculation is made, the scale of the circuit can be decreased and the power consumption can be lowered. Therefore, unlike the case where the calculation is made after A/D conversion, it is possible to avoid a problem that the number of times of calculations and the power consumption are remarkably increased due to increases in the number of dimensions of the input vector and the number of gradations.
摘要翻译：编码装置使用矢量量化编码方法来编码码字的索引，该码字的索引将代码本中的每个代码字的最大标量积的标量量化代码及其最大标量乘积值提供给输入图像的向量分量从图像传感器输入，以输出编码索引。编码装置中的标量乘积值计算电路具有标量积计算部分，其由具有对应于每个码字的代码分量电容器的模拟电路，差分放大器和反馈电容器组成，并且通过标量积计算部分并行计算输入向量的标量乘积值。以这种方式，当进行模拟计算时，可以减小电路的电平并降低功耗。因此，与在A / D转换之后进行计算的情况不同，可以避免由于输入矢量的维数的增加而导致的计算次数和功耗的显着增加的问题，等级数量。

5. 发明授权

US5703503A Winner-take-all circuit 失效
标题翻译：获胜者电路
公开(公告)号：US5703503A
公开(公告)日：1997-12-30
申请号：US653946
申请日：1996-05-22
申请人： Masayuki Miyamoto , Kunihiko Iizuka , Mitsuhiko Fujio , Hirofumi Matsui
发明人： Masayuki Miyamoto , Kunihiko Iizuka , Mitsuhiko Fujio , Hirofumi Matsui
IPC分类号： H03K3/353 , G01R19/00 , H03K3/0233 , H03K17/00 , H03K17/30 , H03K5/22
CPC分类号： G01R19/0038
摘要： A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit. As a result, even when there are fewer k channels receiving input voltages having the highest level and slightly lower ones compared with all the n channels, a feedback current is secured in a sufficient amount to vary the reference voltage. In addition, the winner-take-all circuit of the present invention comprises analog circuits, thereby making the structure simpler compared with a counterpart that processes digital signals.
摘要翻译：用于在输入模拟信号时判断在多个通道中接收具有最大或最小值的模拟信号的通道的获胜者总线电路。每个基本电路包括用于将输入电压与参考电压进行比较的检测单元和用于输出响应于来自检测单元的输出电压确定判定范围的反馈电流的反馈电流产生单元。获胜者总线电路还包括用作所有基本电路的公共晶体管的第十晶体管。即使当输入电压较小时，第十晶体管固定，流过与第七晶体管串联连接的第六晶体管的电流确定来自反馈电流产生电路的反馈电流量。结果，即使当与所有n个通道相比，接收具有最高电平和略微较低的输入电压的k个通道的时候，反馈电流被确保足够的量来改变参考电压。此外，本发明的获胜者总线电路包括模拟电路，从而与处理数字信号的对应物相比，使结构更简单。

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