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    • 7. 发明授权
    • Semiconductor device and method of manufacturing same
    • 半导体装置及其制造方法
    • US07341937B2
    • 2008-03-11
    • US11174595
    • 2005-07-06
    • Koji AritaMasayoshi TagamiHidenobu Miyamoto
    • Koji AritaMasayoshi TagamiHidenobu Miyamoto
    • H01L21/4763
    • H01L21/76811H01L21/76808H01L21/76813
    • Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.
    • 公开了具有精密加工的双镶嵌结构的半导体器件。 半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜,蚀刻停止膜,第二层间膜,第一硬掩模和第二硬掩模而获得的,第二硬掩模形成为具有 沟槽图案。 至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上,使得其整个表面是平坦的。 光致抗蚀剂形成在光吸收牺牲膜上,并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。 使用光致抗蚀剂作为蚀刻掩模,至少吸光牺牲膜,第一硬掩模和第二层间膜被选择性地蚀刻。