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1. 发明授权

US4882710A FIFO memory including dynamic memory elements 失效
标题翻译： FIFO存储器包括动态存储器元件
公开(公告)号：US4882710A
公开(公告)日：1989-11-21
申请号：US94943
申请日：1987-09-09
申请人： Masashi Hashimoto , Sasaki Kenji , Masayoshi Nomura
发明人： Masashi Hashimoto , Sasaki Kenji , Masayoshi Nomura
IPC分类号： G11C11/401 , G06F5/10 , G11C7/00
CPC分类号： G06F5/10 , G11C7/00
摘要： A FIFO memory is provided with individual arrays of dynamic memory cells and includes a dedicated write line buffer memory and a dedicated read line buffer memory operably connected thereto. First and second line buffer memories are also provided in conjunction with the write line buffer memory and the read line buffer memory so as to permit a faster response to the input and output of data with respect to the FIFO memory. Data may be alternately written into either one of the line buffer memories as a lead-in to the subsequent writing of data in the dynamic memory arrays via the write line buffer memory. Data read out from the other line buffer memory may occur simultaneously. The FIFO memory may serve as a video data frame memory for storing a frame of a video screen image. Where video data is continuously written into the FIFO memory, either the preceding video data frame or the current video data frame that is being written is subject to read out depending on the timing of a read reset signal relative to the last write reset signal. The write line buffer memory and the read line buffer memory are operable independently of each other, and may have simultaneous cycle times without any synchronization therebetween. The first and second line buffer memories preferably comprise static type memory elements to facilitate rapid data read out therefrom in response to a read reset signal.
摘要翻译： FIFO存储器具有单独的动态存储器单元阵列，并且包括可操作地连接到其上的专用写行缓冲存储器和专用读行缓冲存储器。第一和第二行缓冲存储器还与写行缓冲存储器和读行缓冲存储器一起提供，以便允许对FIFO存储器的数据的输入和输出的更快的响应。可以将数据交替地写入行缓冲存储器中的任何一个作为通过写行缓冲存储器在动态存储器阵列中随后写入数据的导入。从其他行缓冲存储器读出的数据可能同时发生。 FIFO存储器可以用作存储视频屏幕图像的帧的视频数据帧存储器。在视频数据被连续地写入FIFO存储器的情况下，根据读取复位信号相对于最后写入复位信号的定时，前面的视频数据帧或正被写入的当前视频数据帧被读出。写行缓冲存储器和读行缓冲存储器可彼此独立地操作，并且可以具有同时的周期时间，而在它们之间没有任何同步。第一行缓冲存储器和第二行缓冲存储器优选地包括静态型存储器元件，以便响应读取的复位信号便于从其读出数据。

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