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1. 发明授权

US07429770B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07429770B2
公开(公告)日：2008-09-30
申请号：US11037333
申请日：2005-01-19
申请人： Masaru Kadoshima , Koji Akiyama , Morifumi Ohno
发明人： Masaru Kadoshima , Koji Akiyama , Morifumi Ohno
IPC分类号： H01L29/76 , H01L29/94 , H01L21/338 , H01L21/3205
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/823835 , H01L21/823842 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.
摘要翻译：提供了一种能够在形成栅电极之后降低阈值电压并降低高温热处理的技术。在由半导体衬底的元件隔离区隔离的有源区上形成n型MIS晶体管或p型MIS晶体管。在n型MIS晶体管中，通过栅极绝缘膜形成栅电极，栅电极由硅化铪膜构成。另一方面，在p型MIS晶体管中，通过栅极绝缘膜形成栅电极，栅电极由铂硅化物膜构成。此外，在用于激活注入到源极区域和漏极区域中的杂质的活化退火（热处理）之后，形成栅电极。

2. 发明申请

US20050167762A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050167762A1
公开(公告)日：2005-08-04
申请号：US11037333
申请日：2005-01-19
申请人： Masaru Kadoshima , Koji Akiyama , Morifumi Ohno
发明人： Masaru Kadoshima , Koji Akiyama , Morifumi Ohno
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/823835 , H01L21/823842 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.
摘要翻译：提供了一种能够在形成栅电极之后降低阈值电压并降低高温热处理的技术。在由半导体衬底的元件隔离区隔离的有源区上形成n型MIS晶体管或p型MIS晶体管。在n型MIS晶体管中，通过栅极绝缘膜形成栅电极，栅电极由硅化铪膜构成。另一方面，在p型MIS晶体管中，通过栅极绝缘膜形成栅电极，栅电极由铂硅化物膜构成。此外，在用于激活注入到源极区域和漏极区域中的杂质的活化退火（热处理）之后，形成栅电极。

3. 发明授权

US07579660B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07579660B2
公开(公告)日：2009-08-25
申请号：US11560653
申请日：2006-11-16
申请人： Koji Akiyama , Zhang Lulu , Morifumi Ohno
发明人： Koji Akiyama , Zhang Lulu , Morifumi Ohno
IPC分类号： H01L27/00
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.
摘要翻译：半导体器件包括：表面具有半导体层的基板，配置在半导体层上的栅极绝缘膜，以及配置在栅极绝缘膜上的栅电极。栅极包括由与栅极绝缘膜接触的预定金属的氮化物构成的导电层。导电层通过堆叠由预定金属的氮化物构成的第一膜和由预定金属组成的第二膜，并且通过固相扩散将氮从第一膜扩散到第二膜而形成。

4. 发明申请

US20070126062A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070126062A1
公开(公告)日：2007-06-07
申请号：US11560653
申请日：2006-11-16
申请人： Koji Akiyama , Zhang Lulu , Morifumi Ohno
发明人： Koji Akiyama , Zhang Lulu , Morifumi Ohno
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.
摘要翻译：半导体器件包括：表面具有半导体层的基板，配置在半导体层上的栅极绝缘膜，以及配置在栅极绝缘膜上的栅电极。栅极包括由与栅极绝缘膜接触的预定金属的氮化物构成的导电层。导电层通过堆叠由预定金属的氮化物构成的第一膜和由预定金属组成的第二膜，并且通过固相扩散将氮从第一膜扩散到第二膜而形成。

5. 发明申请

US20080054426A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080054426A1
公开(公告)日：2008-03-06
申请号：US11892518
申请日：2007-08-23
申请人： Morifumi Ohno , Motoki Kobayashi , Makoto Terui , Shinji Ohuchi , Mitsuhiko Ogihara
发明人： Morifumi Ohno , Motoki Kobayashi , Makoto Terui , Shinji Ohuchi , Mitsuhiko Ogihara
IPC分类号： H01L23/12 , H01L21/58
CPC分类号： H01L21/6835 , H01L21/6836 , H01L23/642 , H01L23/645 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/83 , H01L25/16 , H01L25/50 , H01L2221/68318 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24225 , H01L2224/24226 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/73267 , H01L2224/82101 , H01L2224/83192 , H01L2224/83894 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2924/01031 , H01L2924/00012 , H05K3/4661
摘要： With the objective of enabling a reduction in the size of a final semiconductor device and its thinning, and attaining facilitation of a manufacturing process, the semiconductor device includes a circuit chip having a flat mounted surface, a circuit chip smaller in size than the former circuit chip, and a sheet-like support. The latter circuit chip is formed over a substrate and has a flat back surface fixed to the substrate and a flat surface positioned on the side opposite to the back surface. The support is bonded to the surface of the latter circuit chip and supports the latter circuit chip. Then, the back surface of the latter circuit chip supported by the support is peeled from the substrate and pressed against the mounted surface, thereby fixing the back surface of the latter circuit chip and the mounted surface by an intermolecular bonding force (e.g., hydrogen bonding).
摘要翻译：为了能够实现最终的半导体器件的尺寸的减小及其变薄，并且为了便于制造工艺，半导体器件包括具有平坦安装表面的电路芯片，尺寸小于前一电路的电路芯片芯片和片状支撑件。后一电路芯片形成在衬底之上，并且具有固定到衬底的平坦背面和位于与背面相对的一侧的平坦表面。该支撑件粘合到后一电路芯片的表面并支撑后一电路芯片。然后，由支撑体支撑的后一电路芯片的背面从基板剥离并压靠在安装表面上，由此通过分子间结合力（例如，氢键合）固定后一电路芯片的背面和安装表面）。

6. 发明授权

US07928546B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07928546B2
公开(公告)日：2011-04-19
申请号：US11892518
申请日：2007-08-23
申请人： Morifumi Ohno , Motoki Kobayashi , Makoto Terui , Shinji Ohuchi , Mitsuhiko Ogihara
发明人： Morifumi Ohno , Motoki Kobayashi , Makoto Terui , Shinji Ohuchi , Mitsuhiko Ogihara
IPC分类号： H01L23/02
CPC分类号： H01L21/6835 , H01L21/6836 , H01L23/642 , H01L23/645 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/83 , H01L25/16 , H01L25/50 , H01L2221/68318 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24225 , H01L2224/24226 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/73267 , H01L2224/82101 , H01L2224/83192 , H01L2224/83894 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2924/01031 , H01L2924/00012 , H05K3/4661
摘要： With the objective of enabling a reduction in the size of a final semiconductor device and its thinning, and attaining facilitation of a manufacturing process, the semiconductor device includes a circuit chip having a flat mounted surface, a circuit chip smaller in size than the former circuit chip, and a sheet-like support. The latter circuit chip is formed over a substrate and has a flat back surface fixed to the substrate and a flat surface positioned on the side opposite to the back surface. The support is bonded to the surface of the latter circuit chip and supports the latter circuit chip. Then, the back surface of the latter circuit chip supported by the support is peeled from the substrate and pressed against the mounted surface, thereby fixing the back surface of the latter circuit chip and the mounted surface by an intermolecular bonding force (e.g., hydrogen bonding).
摘要翻译：为了能够实现最终的半导体器件的尺寸的减小及其变薄，并且为了便于制造工艺，半导体器件包括具有平坦安装表面的电路芯片，尺寸小于前一电路的电路芯片芯片和片状支撑件。后一电路芯片形成在衬底之上，并且具有固定到衬底的平坦背面和位于与背面相对的一侧的平坦表面。该支撑件粘合到后一电路芯片的表面并支撑后一电路芯片。然后，由支撑体支撑的后一电路芯片的背面从基板剥离并压靠在安装表面上，由此通过分子间结合力（例如，氢键合）固定后一电路芯片的背面和安装表面）。

7. 发明授权

US06433377B1 Chain RAM and method for fabricating the same 失效
标题翻译：链式RAM及其制造方法
公开(公告)号：US06433377B1
公开(公告)日：2002-08-13
申请号：US09947611
申请日：2001-09-07
申请人： Morifumi Ohno
发明人： Morifumi Ohno
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22
摘要： A chain ferroelectric RAM includes a memory cell array having a plurality of memory cell, which connected in series between bit line and a plate line. Each memory cell includes a first ferroelectric capacitor having upper and lower electrodes between which a ferroelectric layer is provided; a second ferroelectric capacitor having upper and lower electrodes between which a ferroelectric layer is provided; and a transistor connected to the upper and lower electrodes of the first and second ferroelectric capacitors. The upper electrode of the first ferroelectric capacitor is connected to the lower electrode of the second ferroelectric capacitor, and the lower electrode of the first ferroelectric capacitor is connected to the upper electrode of the second ferroelectric capacitor in a complimentary manner.
摘要翻译：链式铁电RAM包括具有多个存储单元的存储单元阵列，其串联连接在位线与板线之间。每个存储单元包括具有上电极和下电极的第一铁电电容器，其间设有铁电层; 具有上下电极的第二铁电电容器，其间设置铁电层; 以及连接到第一和第二铁电电容器的上电极和下电极的晶体管。第一强电介质电容器的上部电极与第二强电介质电容器的下部电极连接，第一强电介质电容器的下部电极以互补的方式与第二强电介质电容器的上部电极连接。

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