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1. 发明申请

US20090242963A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090242963A1
公开(公告)日：2009-10-01
申请号：US12234197
申请日：2008-09-19
申请人： Masao SHINGU , Shoko Kikuchi , Akira Takashima , Tsunehiro Ino , Koichi Muraoka
发明人： Masao SHINGU , Shoko Kikuchi , Akira Takashima , Tsunehiro Ino , Koichi Muraoka
IPC分类号： H01L29/792 , H01L29/78 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/31604 , H01L29/513 , H01L29/517 , H01L29/66833
摘要： In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio Si/M at a solid solubility limit of SiO2 composition in a composite oxide including metal element M and Al and set to no more than a number ratio Si/M at the condition that the dielectric constant is equal to the dielectric constant of Al2O3 and so that the number ratio Al/M is set to no less than a number ratio Al/M where the crystallization of an oxide of said metal element M is suppressed due to the Al element and set to no more than a number ratio Al/M where the crystallization of the Al2O3 is suppressed due to the metal element M.
摘要翻译：在半导体器件中，侧壁由SiO 2，SiN或SiON制成，并且顶部绝缘膜或栅极绝缘膜由包括Al，Si和金属元素M的氧化物制成，使得Si / M的数量比设定在包含金属元素M和Al的复合氧化物中SiO 2组成的固溶度极限的Si / M的数量比不小于Si / M，并且在介电常数等于 Al 2 O 3的介电常数和Al / M的数量比被设定为不小于Al / M的数量比，其中所述金属元素M的氧化物的结晶由于Al元素而被抑制，并且设定为不大于由于金属元素M而抑制了Al 2 O 3的结晶化的数值比Al / M

2. 发明申请

US20120025294A1 SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120025294A1
公开(公告)日：2012-02-02
申请号：US13208454
申请日：2011-08-12
申请人： Masao SHINGU , Akira Takashima , Koichi Muraoka
发明人： Masao SHINGU , Akira Takashima , Koichi Muraoka
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/66825
摘要： There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge
摘要翻译：提供一种半导体器件，其中抑制源于上绝缘层和元件隔离绝缘层之间的界面的可靠性的劣化。半导体器件包括：半导体区域; 多个堆叠结构，其各自设置在所述半导体区域上，并且具有依次堆叠的隧道绝缘膜，电荷存储层，上绝缘层和控制电极; 设置在所述多个堆叠结构的侧面上的元件隔离绝缘层; 以及设置在半导体区域和多个堆叠结构中的源极 - 漏极区域。元件隔离绝缘层包括SiO 2，SiN和SiON中的至少一种，上绝缘层是含有选自稀土金属，Y，Zr和Hf中的至少一种金属M的氧化物，Si ，并且沟道长度方向上的电荷存储层，上绝缘层和控制电极的各自的长度Lcharge，Ltop和Lgate满足关系“Lcharge

3. 发明申请

US20120193597A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120193597A1
公开(公告)日：2012-08-02
申请号：US13362832
申请日：2012-01-31
申请人： Masao SHINGU , Akira Takashima , Koichi Muraoka
发明人： Masao SHINGU , Akira Takashima , Koichi Muraoka
IPC分类号： H01L45/00 , H01L27/06 , H01L27/24
CPC分类号： H01L45/1273 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L45/1616 , H01L45/1675
摘要： According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.
摘要翻译：根据一个实施例，非易失性存储器件包括存储器部分。存储部分包括第一绝缘层，第二绝缘层和一对电极。第二绝缘层形成在第一绝缘层上并与第一绝缘层接触。第二绝缘层具有与第一绝缘层的组成不同的组成和与第一绝缘层的相位状态不同的相位状态中的至少一个。一对电极能够使电流通过沿着第一绝缘层和第二绝缘层之间的边界部分的电流路径。通过施加在该对电极之间的电压来改变电流路径的电阻。

4. 发明申请

US20120025297A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120025297A1
公开(公告)日：2012-02-02
申请号：US13204412
申请日：2011-08-05
申请人： Akira TAKASHIMA , Masao SHINGU , Koichi MURAOKA
发明人： Akira TAKASHIMA , Masao SHINGU , Koichi MURAOKA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/02145 , H01L21/02156 , H01L21/02161 , H01L21/28273 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a source region and a drain region provided on a surface area of a semiconductor region, a tunnel insulating film provided on a channel between the source region and the drain region, a charge storage layer provided on the tunnel insulating film, a first dielectric film provided on the charge storage layer and containing lanthanum aluminum silicon oxide or oxynitride, a second dielectric film provided on the first dielectric film and containing oxide or oxynitride containing at least one of hafnium (Hf), zirconium (Zr), titanium (Ti), and a rare earth metal, and a control gate electrode provided on the second dielectric film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括设置在半导体区域的表面区域上的源极区域和漏极区域，设置在源极区域和漏极区域之间的沟道上的隧道绝缘膜，设置有电荷存储层在隧道绝缘膜上，设置在电荷存储层上并含有镧铝氧化物或氧氮化物的第一电介质膜，设置在第一电介质膜上并含有氧化物或氮氧化物的第二电介质膜，其含有铪（Hf），锆（Zr），钛（Ti）和稀土金属，以及设置在第二电介质膜上的控制栅电极。

5. 发明申请

US20110241101A1 SEMICONDUCTOR MEMORY ELEMENT AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器元件和半导体存储器件
公开(公告)号：US20110241101A1
公开(公告)日：2011-10-06
申请号：US12880748
申请日：2010-09-13
申请人： Tsunehiro INO , Daisuke MATSUSHITA , Yasushi NAKASAKI , Masao SHINGU
发明人： Tsunehiro INO , Daisuke MATSUSHITA , Yasushi NAKASAKI , Masao SHINGU
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , B82Y10/00 , B82Y30/00 , H01L27/11578 , H01L27/11582 , H01L29/42348 , H01L29/7923 , H01L29/7926
摘要： According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO2 particles, a block insulator provided on the charge accumulation film, and a control electrode provided on the block insulator.
摘要翻译：根据一个实施例，半导体存储元件包括半导体层，设置在半导体层上的隧道绝缘体，设置在隧道绝缘体上的电荷累积膜，其膜厚度为0.9nm以上且2.8nm以下，电荷积累含有立方HfO 2颗粒的膜，设置在电荷累积膜上的块绝缘体，以及设置在块绝缘体上的控制电极。

6. 发明申请

US20120032248A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT 有权
标题翻译：非易失性半导体存储器元件，非易失性半导体存储器以及用于操作非易失性半导体存储器元件的方法
公开(公告)号：US20120032248A1
公开(公告)日：2012-02-09
申请号：US13272821
申请日：2011-10-13
申请人： Masao SHINGU , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
发明人： Masao SHINGU , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储元件，包括：半导体衬底，包括：源极区; 漏区; 和通道区域; 形成在沟道区上的下绝缘膜; 电荷存储膜，形成在下绝缘膜上并存储数据; 形成在电荷存储膜上的上绝缘膜; 以及形成在所述上绝缘膜上的控制栅极，其中所述上绝缘膜包括：第一绝缘膜; 以及与所述第一绝缘膜层压的第二绝缘膜，并且其中所述第一绝缘膜形成为具有比所述第二绝缘膜的陷阱级密度大的陷阱级密度。

7. 发明申请

US20130010535A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT 有权
公开(公告)号：US20130010535A1
公开(公告)日：2013-01-10
申请号：US13619223
申请日：2012-09-14
申请人： Masao SHINGU , Jun FUJIKI , Naoki YASUDA , Koichi MURAOKA
发明人： Masao SHINGU , Jun FUJIKI , Naoki YASUDA , Koichi MURAOKA
IPC分类号： H01L29/792 , G11C11/40
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

8. 发明申请

US20100034023A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT 有权
标题翻译：非易失性半导体存储器元件，非易失性半导体存储器以及用于操作非易失性半导体存储器元件的方法
公开(公告)号：US20100034023A1
公开(公告)日：2010-02-11
申请号：US12405626
申请日：2009-03-17
申请人： Masao SHINGU , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
发明人： Masao SHINGU , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储元件，包括：半导体衬底，包括：源极区; 漏区; 和通道区域; 形成在沟道区上的下绝缘膜; 电荷存储膜，形成在下绝缘膜上并存储数据; 形成在电荷存储膜上的上绝缘膜; 以及形成在所述上绝缘膜上的控制栅极，其中所述上绝缘膜包括：第一绝缘膜; 以及与所述第一绝缘膜层压的第二绝缘膜，并且其中所述第一绝缘膜形成为具有比所述第二绝缘膜的陷阱级密度大的陷阱级密度。

9. 发明申请

US20130134372A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130134372A1
公开(公告)日：2013-05-30
申请号：US13689026
申请日：2012-11-29
申请人： Kiwamu SAKUMA , Haruka KUSAI , Shosuke FUJII , Li ZHANG , Masahiro KIYOTOSHI , Masao SHINGU
发明人： Kiwamu SAKUMA , Haruka KUSAI , Shosuke FUJII , Li ZHANG , Masahiro KIYOTOSHI , Masao SHINGU
IPC分类号： H01L45/00 , H01L21/265
CPC分类号： H01L27/1157 , H01L21/265 , H01L21/845 , H01L27/11551 , H01L27/11578 , H01L27/1211 , H01L27/2436 , H01L27/2481 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L45/04
摘要： According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.
摘要翻译：根据一个实施例，半导体器件包括第一至第n半导体层（n为等于或大于2的自然数），从绝缘层的表面依次堆叠在与第绝缘层，所述第一至第n半导体层在与所述绝缘层的表面平行的第二方向上延伸，所述第一至第n半导体层彼此绝缘，公共电极连接到所述第一至第n 半导体层，其第二方向的第一端，以及使用第一至第n半导体层作为沟道并选择第一至第n半导体层之一的层选择晶体管。

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