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    • 1. 发明授权
    • Ultrasonic tomography apparatus
    • 超声层析成像仪
    • US4099419A
    • 1978-07-11
    • US773171
    • 1977-03-01
    • Masao KurodaToshio KondoToshio OgawaSekijyuro Ono
    • Masao KurodaToshio KondoToshio OgawaSekijyuro Ono
    • A61B8/14A61B8/00G01N29/06G01N29/24G01R13/20G01S7/52G01N29/00
    • G01N29/06G01S7/52046
    • There is disclosed an ultrasonic tomography apparatus of electronic scanning type in which an array of ultrasonic transducer elements are excited with desired time delays allotted for the transducer elements thereby to transmit and receive ultrasonic beams at a deflection angle corresponding to the desired time delays, and the received echo signal of the ultrasonic beams is displayed on a CRT display device in a form of a tomograph of a sample to which the ultrasonic beams are directed. The apparatus comprises a memory in which both of first signals representative of the time delays given to the transducer elements in dependence on given deflection angles and signals designating display position in the X- and Y-directions of the CRT are previously stored and read out for producing delays allotted for the transducer elements and displaying the received echo signal on the CRT.
    • 公开了一种电子扫描型超声波断层摄影装置,其中以期望的时间延迟激励超声波换能器元件阵列,从而以对应于期望的时间延迟的偏转角发送和接收超声波束,并且 超声波束的接收回波信号以超声波束所指向的样本的断层图的形式显示在CRT显示装置上。 该装置包括存储器,其中预先存储表示根据给定偏转角给予换能器元件的时间延迟的两个第一信号和指示CRT的X和Y方向上的显示位置的信号,并读出以供 产生分配给换能器元件的延迟并在CRT上显示所接收的回波信号。
    • 3. 发明授权
    • Electrically adjustable delay circuit and ultrasonic diagnosis apparatus
    • 电动调节延时电路及超声波诊断仪
    • US5318034A
    • 1994-06-07
    • US982558
    • 1992-11-27
    • Kazunari IshidaKazutaka OkadaToshio KondoToshio OgawaNorio YokozawaTakashi Ichikawa
    • Kazunari IshidaKazutaka OkadaToshio KondoToshio OgawaNorio YokozawaTakashi Ichikawa
    • G01S7/52A61B8/00
    • G01S7/52046
    • This invention provides a delay circuit capable of electrically varying the delay amount comprising a first transistor for receiving a signal to be delayed from the base connected to an input terminal and outputting a positive phase signal and a negative phase signal with respect to the signal from the input terminal, respectively from the emitter and the collector thereof; two variable capacity diodes with their terminals of the same polarity connected together and a specified control voltage applied to the point of said connection, one end of the connected diodes being connected to the emitter of said first transistor; a second transistor with the base grounded, the emitter connected to the collector of the above-mentioned first transistor, and the collector connected to one end of a specified resistance; and a delayed signal output terminal having connected thereto the other end of the two variable capacity diodes and the other end of the specified resistance. According to this invention, an ultrasonic diagnosis apparatus using this delay circuit is also provided.
    • 本发明提供一种延迟电路,其能够电延迟量,包括第一晶体管,用于接收从连接到输入端子的基极延迟的信号,并输出正相信号和负相位信号 分别从发射极和集电极输出端子; 两个具有相同极性的端子的可变容量二极管连接在一起,并且将指定的控制电压施加到所述连接点,所连接的二极管的一端连接到所述第一晶体管的发射极; 第二晶体管,其基极接地,发射极连接到上述第一晶体管的集电极,并且集电极连接到指定电阻的一端; 以及延迟信号输出端子,其连接到两个可变容量二极管的另一端和指定电阻的另一端。 根据本发明,还提供了使用该延迟电路的超声波诊断装置。
    • 4. 发明授权
    • Delay circuit of ultrasonic diagnostic apparatus using delay line
comprising variable capacitance diode and inductor
    • 使用包括可变电容二极管和电感器的延迟线的超声波诊断装置的延迟电路
    • US5146192A
    • 1992-09-08
    • US727053
    • 1991-07-08
    • Toshio KondoToshio OgawaKazunari IshidaAkihiro Ueyama
    • Toshio KondoToshio OgawaKazunari IshidaAkihiro Ueyama
    • H03H11/26
    • H03H11/265
    • A delay circuit of ultrasonic diagnostic apparatus comprising a delay line consisting of a plurality of unit portions connected in cascade, in each of which an anode of a first variable capacitance diode and a cathode of a second variable capacitance diode are connected with a connecting point of two inductors connected in series, or a delay line obtained by replacing capacitances in a second order all pass type delay line by variable capacitance diodes, or a delay line, in which variable capacitance diodes and inductors form a balanced circuit; and control circuit for applying a reverse bias voltage to each of the variable capacitance diodes; and an amplifier or a variable resistance circuit using FETs serving as a matching circuit for the delay line, capable of varying continuously an input impedance by using a control voltage from the exterior.
    • 一种超声波诊断装置的延迟电路,包括由串联连接的多个单位部分构成的延迟线,其中,第一可变电容二极管的阳极和第二可变电容二极管的阴极分别与 串联连接的两个电感器或通过用二次替换电容获得的延迟线通过可变电容二极管或延迟线全部通过类型延迟线,其中可变电容二极管和电感器形成平衡电路; 以及用于向每个可变电容二极管施加反向偏置电压的控制电路; 以及使用用作延迟线的匹配电路的FET的放大器或可变电阻电路,能够通过使用来自外部的控制电压来连续地改变输入阻抗。
    • 6. 发明申请
    • TWO-PART HAIR DYE
    • 两部分头发染发剂
    • US20120284932A1
    • 2012-11-15
    • US13509735
    • 2010-11-30
    • Yuki NaoiYoshinori SaitoToshio Ogawa
    • Yuki NaoiYoshinori SaitoToshio Ogawa
    • A61K8/04A61Q5/10
    • A61Q5/10A61K8/046A61K8/342A61K8/86A61K2800/88
    • A two-part hair dye including a first part containing an alkali agent, a second part containing hydrogen peroxide, and a non-aerosol foamer container; wherein a liquid mixture contains Components (A) and (B) specified below, wherein the content of hydrogen peroxide in the liquid mixture is 3.60 mass % or higher, and the viscosity of the liquid mixture is 1 to 300 mPa·s.A method for dying hair, wherein a foam of the liquid mixture of the first part and the second part of the two-part hair dye is applied to hair, left to stand for 3 to 60 minutes, and then washed out.Component (A): oxidation dye;Component (B): 0.50 to 3.0 mass %, of polypropylene glycol having a weight-average molecular weight of 200 to 800.
    • 包括含有碱剂的第一部分,含有过氧化氢的第二部分和非气溶胶发泡剂容器的两部分染发剂; 其中,液体混合物含有下述的成分(A)和(B),其中,液体混合物中过氧化氢的含量为3.60质量%以上,液体混合物的粘度为1〜300mPa·s。 一种染色头发的方法,其中将两部分染发剂的第一部分和第二部分的液体混合物的泡沫施加到头发上,静置3至60分钟,然后洗掉。 组分(A):氧化染料; 成分(B):0.50〜3.0质量%的重均分子量为200〜800的聚丙二醇。
    • 8. 发明授权
    • Logical circuit device, logical operation varying method, and logical operation system
    • 逻辑电路设备,逻辑运算变化方法和逻辑运算系统
    • US07969185B2
    • 2011-06-28
    • US12398204
    • 2009-03-05
    • Toshio Ogawa
    • Toshio Ogawa
    • H03K19/173
    • H03K19/17776H03K19/1736H03K19/17728H03K19/17748H03K19/17752H03K19/17756
    • A logical circuit device comprises a plurality of logical blocks including reconfigurable logical configurations and a network including reconfigurable connections among the plurality of logical blocks, wherein at least one of the plurality of logical blocks comprises a basic logical operation element. The basic logical operation element receives a first data signal and a first validity indication signal that becomes an asserted state when the first data signal is valid, outputs a second data signal generated by a first logical operation based on the first data signal and a second validity indication signal that becomes an asserted state when the second data signal is valid, and sets the second data signal to the asserted state in response to the asserted state of the first validity indication signal.
    • 逻辑电路装置包括多个逻辑块,包括可重新配置的逻辑配置和包括多个逻辑块之间的可重配置连接的网络,其中多个逻辑块中的至少一个包括基本逻辑运算元件。 基本逻辑运算元件接收第一数据信号和第一有效指示信号,当第一数据信号有效时,第一数据信号和第一有效性指示信号变为有效状态,基于第一数据信号输出由第一逻辑运算产生的第二数据信号和第二有效值 指示信号在第二数据信号有效时变为有效状态,并且响应于第一有效指示信号的有效状态将第二数据信号设置为置位状态。