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1. 发明授权

US5303236A Signalling apparatus for use in an ATM switching system 失效
标题翻译：用于ATM交换系统的信令装置
公开(公告)号：US5303236A
公开(公告)日：1994-04-12
申请号：US780811
申请日：1991-10-22
申请人： Masao Kunimoto , Jiro Kashio , Makoto Mori , Shinobu Gohara
发明人： Masao Kunimoto , Jiro Kashio , Makoto Mori , Shinobu Gohara
IPC分类号： G06F5/06 , H04J3/24 , H04L12/56 , H04Q11/04 , H04L12/24
CPC分类号： H04L12/5601 , G06F5/065 , H04J3/247 , H04L49/104 , H04L49/1553 , H04Q11/0457 , H04Q11/0478 , G06F2205/066 , H04L2012/563 , H04L2012/5646 , H04L2012/5652 , H04Q2213/107 , H04Q2213/29
摘要： A subscriber line signalling apparatus for use in an asynchronous mode communication system includes a switching circuit having a plurality of input terminals and a plurality of output terminals. The switching circuit selectively communicates fixed length information packets to an adaptation processing unit. The adaptation processing unit reassembles the fixed length packets to signalling frames, and transmits them to a frame processor.
摘要翻译：用于异步模式通信系统的用户线信令装置包括具有多个输入端和多个输出端的开关电路。切换电路选择性地将固定长度信息分组传送到适配处理单元。适配处理单元将固定长度分组重新组合到信令帧，并将它们发送到帧处理器。

2. 发明授权

US5101404A Signalling apparatus for use in an ATM switching system 失效
标题翻译：用于ATM交换系统的信令装置
公开(公告)号：US5101404A
公开(公告)日：1992-03-31
申请号：US397048
申请日：1989-08-21
申请人： Masao Kunimoto , Jiro Kashio , Makoto Mori , Shinobu Gohara
发明人： Masao Kunimoto , Jiro Kashio , Makoto Mori , Shinobu Gohara
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/104 , H04Q11/0457 , H04Q11/0478 , H04L2012/563 , H04Q2213/107 , H04Q2213/29
摘要： A subscriber line signalling apparatus for use in an asynchronous mode communication system includes a switching circuit having a plurality of input terminals and a plurality of output terminals. The switching circuit selectively communicates fixed length information packets to an adaptation processing unit. The adaptation processing unit reassembles the fixed length packets to signalling frames, and transmits them to a frame processor.
摘要翻译：用于异步模式通信系统的用户线信令装置包括具有多个输入端和多个输出端的开关电路。切换电路选择性地将固定长度信息分组传送到适配处理单元。适配处理单元将固定长度分组重新组合到信令帧，并将它们发送到帧处理器。

3. 发明授权

US5214642A ATM switching system and adaptation processing apparatus 失效
标题翻译： ATM交换系统和适配处理设备
公开(公告)号：US5214642A
公开(公告)日：1993-05-25
申请号：US645041
申请日：1991-01-23
申请人： Masao Kunimoto , Jiro Kashio , Kenji Kawakita , Shinobu Gohara , Shinichi Iwaki , Hiroyuki Ichikawa
发明人： Masao Kunimoto , Jiro Kashio , Kenji Kawakita , Shinobu Gohara , Shinichi Iwaki , Hiroyuki Ichikawa
IPC分类号： G06F5/06 , H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L49/254 , G06F5/065 , H04J3/247 , H04L49/1553 , H04L49/30 , H04L49/555 , H04Q11/0478 , G06F2205/066 , H04L2012/563 , H04L2012/5652 , H04L49/3009
摘要： An adaptation processing apparatus for assembling received data units of a fixed length to provide variable length data units and transmitting the variable length data units to a plurality of variable length data unit processors while assembling variable length data units received from said plurality of the variable length data unit processors to provide fixed length data units for transmission thereof. An ATM switching system includes the adaptation processing apparatus, a signal processing unit including the plurality of variable length data unit processors mentioned above, and first-in first-out mechanisms for the variable length data units provided in the adaptation processing apparatus in association with every one of the plural variable length data unit processors.
摘要翻译：一种用于组合固定长度的接收数据单元以提供可变长度数据单元并且将可变长度数据单元发送到多个可变长度数据单元处理器的适配处理装置，同时组装从所述多个可变长度数据接收的可变长度数据单元单元处理器以提供用于其传输的固定长度数据单元。 ATM交换系统包括自适应处理装置，包括上述多个可变长度数据单元处理器的信号处理单元，以及在适配处理装置中提供的可变长度数据单元的先进先出机制，与每个多个可变长度数据单元处理器中的一个。

4. 发明授权

US5090011A Packet congestion control method and packet switching equipment 失效
标题翻译： PACKET CONGESTION控制方法和分组开关设备
公开(公告)号：US5090011A
公开(公告)日：1992-02-18
申请号：US455135
申请日：1989-12-21
申请人： Isao Fukuta , Kenji Kawakita , Jiro Kashio , Yutaka Torii , Shinobu Gohara , Noboru Endo
发明人： Isao Fukuta , Kenji Kawakita , Jiro Kashio , Yutaka Torii , Shinobu Gohara , Noboru Endo
IPC分类号： H04Q3/00 , H04L12/801 , H04L12/911
CPC分类号： H04L12/5602 , H04L49/3081 , H04L2012/5635 , H04L2012/5636 , H04L2012/5652
摘要： A packet switching equipment housing therein a plurality of pairs of an input line and an output line is provided with a monitor circuit for monitoring a packet congestion state in the packet switching equipment for each output line. When a packet congestion is detected in association with either one of the output lines, a congestion indicator is added to a packet to be delivered to the output line so as to return the packet as a congestion notice packet to an equipment as the transmission source of the packet; furthermore, the input packet is relayed via the output line to the destination equipment.

5. 发明授权

US06728242B2 ATM cell switching system 失效
标题翻译： ATM信元交换系统
公开(公告)号：US06728242B2
公开(公告)日：2004-04-27
申请号：US10374998
申请日：2003-02-28
申请人： Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
发明人： Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元表装置。

6. 发明授权

US5467346A Packet communication method and packet communication apparatus 失效
标题翻译：分组通信方法和分组通信装置
公开(公告)号：US5467346A
公开(公告)日：1995-11-14
申请号：US266636
申请日：1994-06-28
申请人： Yutaka Ito , Makoto Mori , Shinobu Gohara
发明人： Yutaka Ito , Makoto Mori , Shinobu Gohara
IPC分类号： H04L12/70 , H04L12/803 , H04L12/891 , H04Q11/04
CPC分类号： H04L49/3081 , H04Q11/0478 , H04L2012/5612 , H04L2012/5613 , H04L2012/5615 , H04L2012/5672
摘要： In communication nodes inserted in a ring-shaped or bus-shaped transmission path, a transmitting section writes transmission packets into transmission buffers in a predetermined order and sends out the transmission packets in the predetermined order onto the transmission path at appropriate unoccupied time of the transmission path, whereas a receiving section temporarily stores packets directed to its own node into a receiving buffer and reads out the packets in the same order as that of writing them into the transmission buffers in the transmitting section.
摘要翻译：在插入环形或总线形传输路径的通信节点中，发送部分以预定的顺序将传输分组写入传输缓冲器，并在传输的适当的未占用时间以预定顺序发送传输分组到传输路径上而接收部分将指向其自己的节点的分组临时存储到接收缓冲器中，并以与将它们写入发送部分中的传输缓冲器的顺序相同的顺序读出分组。

7. 发明授权

US4956839A ATM switching system 失效
标题翻译： ATM交换系统
公开(公告)号：US4956839A
公开(公告)日：1990-09-11
申请号：US382419
申请日：1989-07-20
申请人： Yutaka Torii , Makoto Mori , Shinobu Gohara , Kenichi Ohtsuki , Yoshito Sakurai
发明人： Yutaka Torii , Makoto Mori , Shinobu Gohara , Kenichi Ohtsuki , Yoshito Sakurai
IPC分类号： H04L12/70 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937
CPC分类号： H04L49/309 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/503 , H04L2012/5636 , H04L2012/5674 , H04L49/1507 , H04L49/254 , Y10S370/905
摘要： In the ATM switching system, an ATM speech path is divided into a plurality of functional blocks. A routing function for distributing cells (packets) each of a fixed length to addresses outgoing lines and a logical multiplexing function are imparted to a switch, while other functions associated with a line typified by a phase synchronizing function and a flow control function are incorporated en bloc in ATM line terminating units and functions capable of being processed by hardware in common to the lines are assembled in a line common unit. The ATM line terminating unit physically terminates transmission lines and performs the processing relevant to header information of the cells each of a fixed length (ATM terminating processing) and includes a cell phase synchronizing circuit for matching the temporal positions of the cells among the lines and a flow control circuit for avoiding overload exceeding the load declared by subscriber terminal. The line common unit serves for processings of call control signals and the calls and includes a signal processing circuit and a control circuit. The switch performs cell multiplexing and switching and is constituted by a self-routing switch.

8. 发明授权

US06546011B1 ATM cell switching system 失效
标题翻译： ATM信元交换系统
公开(公告)号：US06546011B1
公开(公告)日：2003-04-08
申请号：US09804225
申请日：2001-03-13
申请人： Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
发明人： Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要： An ATM switching system including a switch unit having a plurality of input ports and output ports, and a multiplexer for multiplexing cell trains from at least two output ports into a single cell train and outputting the cell train to and output port. A demultiplexer can be provided in place of the multiplexer. The switch unit includes a buffer memory for storing cells from the input ports while forming a queue chain for each output port, a demultiplexer for distributing the cells from the buffer memory to output ports, and a buffer memory control circuit for controlling write and read operations of the buffer memory. The buffer memory control circuit has a control table for outputting an identifier of an output port the cells read from the buffer memory are to be output. Cells are read from the chain designated by the identifier.
摘要翻译：一种ATM交换系统，包括具有多个输入端口和输出端口的开关单元，以及多路复用器，用于将来自至少两个输出端口的单元列多路复用为单个单元列，并将该单元列输出到输出端口。可以提供多路分解器来代替多路复用器。开关单元包括用于存储来自输入端口的单元的缓冲存储器，同时为每个输出端口形成一个队列链;用于将单元从缓冲存储器分配到输出端口的解复用器，以及用于控制写和读操作的缓冲存储器控制电路的缓冲存储器。缓冲存储器控制电路具有用于输出要从缓冲存储器读取的单元被输出的输出端口的标识符的控制表。从由标识符指定的链中读取单元。

9. 发明授权

US5386415A Packet communiction method and packet communication apparatus 失效
标题翻译：分组通信方法和分组通信装置
公开(公告)号：US5386415A
公开(公告)日：1995-01-31
申请号：US789001
申请日：1991-11-07
申请人： Yutaka Ito , Makoto Mori , Shinobu Gohara
发明人： Yutaka Ito , Makoto Mori , Shinobu Gohara
IPC分类号： H04L12/70 , H04L12/803 , H04L12/891 , H04Q11/04
CPC分类号： H04L49/3081 , H04Q11/0478 , H04L2012/5612 , H04L2012/5613 , H04L2012/5615 , H04L2012/5672
摘要： In communication nodes inserted in a ring-shaped or bus-shaped transmission path, a transmitting section writes transmission packets into transmission buffers in appropriate order and sends out the transmission packets onto the transmission path at appropriate unoccupied time of the transmission path, whereas a receiving section temporarily stores packets directed to its own node into a receiving buffer and reads out the packets in the same order as that of writing them into the transmission buffers in the transmitting section. Further, in the transmitting section, special packets referred to as "restart cells" are inserted on all of the transmission paths or written into all transmitting buffers at intervals of a fixed period. In the receiving section, when the restart cell is received on a certain transmission path, readout of packets arriving at that transmission path is temporarily stopped. After restart cells have arrived at all transmission paths, readout is reopened from the first transmission path of the order.
摘要翻译：在插入环形或总线形传输路径的通信节点中，发送部分以适当的顺序将传输分组写入传输缓冲器，并在发送路径的适当未占用时间将传输分组发送到传输路径上，而接收将定向到其自身节点的分组临时存储到接收缓冲器中，并以与将它们写入发送部分中的发送缓冲器的顺序相同的顺序读出分组。此外，在发送部分中，称为“重新启动小区”的特殊分组被插入到所有传输路径上或以固定周期的间隔写入所有发送缓冲器。在接收部分中，当在某个传输路径上接收到重新启动信元时，暂时停止到达该传输路径的分组的读出。在重新启动之后，单元已经到达所有的传输路径，从该顺序的第一个传输路径重新读出。

10. 发明授权

US4910731A Switching system and method of construction thereof 失效
标题翻译：开关系统及其构造方法
公开(公告)号：US4910731A
公开(公告)日：1990-03-20
申请号：US218217
申请日：1988-07-13
申请人： Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
发明人： Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
IPC分类号： H04L12/54 , H04L12/70 , H04L12/933 , H04L12/947 , H04Q11/04
CPC分类号： H04L12/5601 , H04L12/5602 , H04L49/108 , H04L49/1569 , H04L49/256 , H04Q11/0478 , H04L2012/565 , H04L2012/5652 , H04L2012/5681
摘要： A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

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