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1. 发明授权

US07002043B2 Process for producing 1,1,1-trifluoroacetone 失效
标题翻译：制备1,1,1-三氟丙酮的方法
公开(公告)号：US07002043B2
公开(公告)日：2006-02-21
申请号：US10448318
申请日：2003-05-30
申请人： Masanori Tsukamoto , Fumiyoshi Yoshikawa , Masataka Fujimoto , Naoto Takada , Yoshikazu Sugimori , Junji Negishi
发明人： Masanori Tsukamoto , Fumiyoshi Yoshikawa , Masataka Fujimoto , Naoto Takada , Yoshikazu Sugimori , Junji Negishi
IPC分类号： C07C45/65
CPC分类号： C07C49/167 , C07C45/65
摘要： The invention relates to a process for producing 1,1,1-trifluoroacetone, which is useful as an intermediate of pharmaceuticals and agricultural chemicals, or as a reagent for introducing fluorine-containing groups. This process includes the step of conducting a hydrogenolysis of a halogenated trifluoroacetone, which is represented by the formula [1], by a hydrogen gas, in a liquid phase containing water, in the presence of a catalyst containing a transition metal, where X represents a chlorine, bromine or iodine, and n represents an integer from 1 to 3. It is possible by the process to easily produce 1,1,1-trifluoroacetone with high purity.
摘要翻译：本发明涉及一种生产1,1,1-三氟丙酮的方法，其可用作药物和农药的中间体，或用作引入含氟基团的试剂。该方法包括在含有过渡金属的催化剂的存在下，通过氢气在含有水的液相中，通过式[1]表示的卤代三氟丙酮的氢解，步骤 =“CHEM-US-00001”num =“000

2. 发明授权

US06774266B2 Process for producing 1,1,1-trifluoroacetone 失效
标题翻译：制备1,1,1-三氟丙酮的方法
公开(公告)号：US06774266B2
公开(公告)日：2004-08-10
申请号：US10299996
申请日：2002-11-20
申请人： Masanori Tsukamoto , Takashi Sakaya , Takayuki Nishimiya , Junji Negishi
发明人： Masanori Tsukamoto , Takashi Sakaya , Takayuki Nishimiya , Junji Negishi
IPC分类号： C07C4500
CPC分类号： C07C45/65 , C07C49/167
摘要： A process for producing 1,1,1-trifluoroacetone includes the step of conducting in a gas phase a hydrogenolysis of a tetrafluoroacetone, which is represented by the general formula [1], by a hydrogen gas in the presence of a catalyst containing a transition metal, where X represents a chlorine, bromine or iodine, and n represents an integer from 0 to 2.
摘要翻译：制备1,1,1-三氟丙酮的方法包括在含有过渡金属催化剂的催化剂存在下，在气相中进行由通式[1]表示的四氟丙酮的氢解的工序，金属，其中X表示氯，溴或碘，n表示0至2的整数。

3. 发明申请

US20080087966A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080087966A1
公开(公告)日：2008-04-17
申请号：US11869882
申请日：2007-10-10
申请人： Kaori Tai , Masanori Tsukamoto , Masashi Nakata , Itaru Oshiyama
发明人： Kaori Tai , Masanori Tsukamoto , Masashi Nakata , Itaru Oshiyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823871 , H01L29/66545
摘要： Disclosed herein is a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.
摘要翻译：本文公开了一种包括N沟道绝缘栅场效应晶体管和P沟道绝缘栅场效应晶体管的半导体器件，该器件具有：第一绝缘层和第二绝缘层; 和栅电极接触插头。 N沟道绝缘栅场效应晶体管的栅电极和P沟绝缘栅场效应晶体管的每一个都被埋在设置在第一绝缘层中的栅电极形成开口中。

4. 发明申请

US20100148274A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100148274A1
公开(公告)日：2010-06-17
申请号：US12712809
申请日：2010-02-25
申请人： Kaori Tai , Masanori Tsukamoto , Masashi Nakata , Itaru Oshiyama
发明人： Kaori Tai , Masanori Tsukamoto , Masashi Nakata , Itaru Oshiyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823871 , H01L29/66545
摘要： A semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.
摘要翻译：一种包括N沟道绝缘栅场效应晶体管和P沟道绝缘栅场效应晶体管的半导体器件，该器件具有：第一绝缘层和第二绝缘层; 和栅电极接触插头。 N沟道绝缘栅场效应晶体管的栅电极和P沟绝缘栅场效应晶体管的每一个都被埋在设置在第一绝缘层中的栅电极形成开口中。

5. 发明申请

US20110309451A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20110309451A1
公开(公告)日：2011-12-22
申请号：US13116727
申请日：2011-05-26
申请人： Masanori Tsukamoto
发明人： Masanori Tsukamoto
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28114 , H01L21/823842 , H01L21/823871 , H01L29/42376 , H01L29/66545 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a semiconductor device includes: forming a first gate insulating film on a semiconductor substrate in first and second regions in an active area; forming first gate electrodes on the first gate insulating film in the first and second regions; forming source/drain regions by introducing impurities at both sides of the first gate electrode in the first and second regions; performing heat treatment of activating the impurities; forming a stress liner film so as to cover the whole surface of first gate electrodes in the first and second regions; removing the stress liner film at an upper portion of the first gate electrode in the second region while allowing the stress liner film at least at a portion in the first region to remain to expose the upper portion of the first gate electrode in the second region; forming a groove by removing the first gate electrode in the second region; and forming a second gate electrode in the groove.
摘要翻译：半导体器件的制造方法包括：在有源区域中的第一和第二区域中的半导体衬底上形成第一栅极绝缘膜; 在所述第一和第二区域中的所述第一栅极绝缘膜上形成第一栅电极; 通过在第一和第二区域中的第一栅电极的两侧引入杂质来形成源/漏区; 进行活化杂质的热处理; 形成应力衬垫膜，以覆盖第一和第二区域中的第一栅电极的整个表面; 在所述第二区域中移除所述第一栅电极的上部处的所述应力衬垫膜，同时使所述应力衬垫膜至少在所述第一区域的一部分处保持暴露于所述第二区域中的所述第一栅电极的上部; 通过去除所述第二区域中的所述第一栅极电极而形成沟槽; 以及在所述凹槽中形成第二栅电极。

6. 发明授权

US07714393B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714393B2
公开(公告)日：2010-05-11
申请号：US11869882
申请日：2007-10-10
申请人： Kaori Tai , Masanori Tsukamoto , Masashi Nakata , Itaru Oshiyama
发明人： Kaori Tai , Masanori Tsukamoto , Masashi Nakata , Itaru Oshiyama
IPC分类号： H01L27/088
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823871 , H01L29/66545
摘要： Disclosed herein is a semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the device having: a first insulating layer and a second insulating layer; and gate electrode contact plugs. Each of the gate electrodes of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor is buried in a gate electrode formation opening provided in the first insulating layer.
摘要翻译：本文公开了一种包括N沟道绝缘栅场效应晶体管和P沟道绝缘栅场效应晶体管的半导体器件，该器件具有：第一绝缘层和第二绝缘层; 和栅电极接触插头。 N沟道绝缘栅场效应晶体管的栅电极和P沟绝缘栅场效应晶体管的每一个都被埋在设置在第一绝缘层中的栅电极形成开口中。

7. 发明授权

US6124187A Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6124187A
公开(公告)日：2000-09-26
申请号：US777814
申请日：1996-12-31
申请人： Masanori Tsukamoto
发明人： Masanori Tsukamoto
IPC分类号： H01L21/26 , H01L21/265 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L21/425
CPC分类号： H01L21/28211 , H01L21/28061 , H01L21/28176 , H01L21/823842
摘要： In a method of fabricating a semiconductor device having an N.sup.+ -type layer or P.sup.+ -type layer containing an impurity in a concentration of 1.times.10.sup.19 /cm.sup.3 or more, or a semiconductor device having a silicon based gate electrode structure containing an impurity, the final one of heat treatments each exerting an effect to an active state of the impurity is a high rapid thermal anneal, to thereby suppress an increase in resistance of the N.sup.+ -type layer or P.sup.+ -type layer as a diffusion layer or improve depletion of a poly-Si based gate electrode without occurrence of variations in threshold voltage.
摘要翻译：在制造具有浓度为1×1019 / cm3以上的杂质的N +型层或P +型层的半导体器件的制造方法中，或者是具有含有杂质的硅系栅电极结构的半导体器件，每个对杂质的活性状态产生影响的热处理是高速快速热退火，从而抑制作为扩散层的N +型层或P +型层的电阻增加或改善多晶硅层的消耗， Si基栅电极，而不会发生阈值电压的变化。

8. 发明授权

US5723356A Fabrication method for semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5723356A
公开(公告)日：1998-03-03
申请号：US688117
申请日：1996-07-29
申请人： Masanori Tsukamoto
发明人： Masanori Tsukamoto
IPC分类号： H01L21/265 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L21/70
CPC分类号： H01L21/823835 , H01L21/28061
摘要： A first Poly-Si film and an a-Si film are formed on a semiconductor base body at a first step, and phosphorus ions (N-type impurity) are implanted in the a-Si film at an NMOS forming region and boron ions (P-type impurity) are implanted in the a-Si film at a PMOS forming region at a second step. The a-Si film is crystallized to form a second Poly-Si film and at the same time the impurities are diffused in the second Poly-Si film thus obtained and the first Poly-Si film at a third step. After that, a WSi.sub.x film is formed on the second Poly-Si film at a fourth step, and an offset oxide film is formed on the WSi.sub.x film at a fifth step. With this method, it is possible to suppress mutual diffusion of impurities having conducting types different from each other and hence to fabricate a semiconductor device such as a CMOS, which is low in variations in threshold voltage and excellent in device characteristics.
摘要翻译：首先在半导体基体上形成第一多晶硅膜和a-Si膜，在NMOS形成区域的a-Si膜中注入磷离子（N型杂质），将硼离子 P型杂质）在第二步骤的PMOS形成区域注入到a-Si膜中。使a-Si膜结晶化，形成第二多晶硅膜，同时在第三步骤中杂质扩散到如此获得的第二多晶硅膜和第一多晶硅膜中。之后，在第四步上在第二多晶硅膜上形成WSix膜，第五步在WSix膜上形成偏移氧化物膜。利用这种方法，可以抑制具有彼此不同的导电类型的杂质的相互扩散，从而制造阈值电压变化低，器件特性优异的诸如CMOS的半导体器件。

9. 发明授权

US5700349A Method for forming multi-layer interconnections 失效
标题翻译：形成多层互连的方法
公开(公告)号：US5700349A
公开(公告)日：1997-12-23
申请号：US585772
申请日：1996-01-16
申请人： Masanori Tsukamoto , Tetsuo Gocho
发明人： Masanori Tsukamoto , Tetsuo Gocho
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/00
CPC分类号： H01L21/76897 , H01L21/76834 , H01L2924/0002
摘要： A method of forming a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-hole is used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etch stop layer covering the entire surface of the substrate, said etching stop layer being slower in etch rate than said interlayer insulating film; anisotropically etching said interlayer insulating film in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material.
摘要翻译：一种形成多层互连的方法，其中在位于两个相邻的中间互连层之间的层间绝缘层中形成通孔，该通孔用于在上互连层和下互连层之间建立电互连，所述方法包括以下步骤在所述中间互连层上形成偏移绝缘膜，使得中间互连层和偏移绝缘膜的图案相同; 在由所述中间互连层和所述偏移绝缘膜构成的图案的侧壁表面上形成侧壁绝缘膜; 基本上保形地形成覆盖衬底的整个表面的蚀刻停止层，所述蚀刻停止层的蚀刻速率比所述层间绝缘膜慢; 在开口尺寸小于互连层之间的间隔的区域中各向异性地蚀刻所述层间绝缘膜; 选择性地去除暴露在所述区域的底表面上的用于完成通孔的蚀刻停止层; 并用导电材料填充所述通孔。

10. 发明授权

US5643833A Method of making a contact hole in a semiconductor device 失效
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US5643833A
公开(公告)日：1997-07-01
申请号：US495268
申请日：1995-06-27
申请人： Masanori Tsukamoto
发明人： Masanori Tsukamoto
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L29/78
CPC分类号： H01L21/31144 , H01L21/76897
摘要： A method of manufacturing a semiconductor device with multi-layer interconnections is disclosed. The method includes the steps of: forming a first electrically conductive interconnection layer on an insulating layer formed on a lower interconnection layer; forming an insulating layer on the first electrically conductive interconnection layer; forming an antireflection layer on the insulating layer; patterning the first electrically conductive interconnection layer, the insulating layer and the antireflection layer to form a stacked film composed of the first electrically conductive interconnection layer, the insulating layer and the antireflection layer; forming a sidewall on the stacked film; forming an interlayer insulating layer on entire surface of the stacked film having the sidewall formed thereon and the insulating layer; forming a contact hole to expose a selected portion of the lower interconnection layer using the sidewall as a mask; and depositing a second electrically conductive interconnection layer in the contact hole at the exposed portion of the lower interconnection layer.
摘要翻译：公开了一种制造具有多层互连的半导体器件的方法。该方法包括以下步骤：在形成在下互连层上的绝缘层上形成第一导电互连层; 在所述第一导电互连层上形成绝缘层; 在绝缘层上形成抗反射层; 图案化第一导电互连层，绝缘层和抗反射层，以形成由第一导电互连层，绝缘层和抗反射层构成的叠层膜; 在所述层叠膜上形成侧壁; 在其侧壁形成的层叠膜的整个表面上形成层间绝缘层和绝缘层; 形成接触孔，以使用所述侧壁作为掩模来暴露所述下互连层的选定部分; 以及在所述下互连层的暴露部分的所述接触孔中沉积第二导电互连层。

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