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    • 4. 发明授权
    • Digital frequency/phase locked loop
    • 数字频率/锁相环
    • US08508303B2
    • 2013-08-13
    • US13256748
    • 2010-02-05
    • Masakatsu Maeda
    • Masakatsu Maeda
    • H03L7/099
    • H03L7/107H03L7/093H03L7/099H03L7/1075H03L2207/06H03L2207/50
    • A digital FLL/PLL is provided which is capable of converging an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor corresponding to each VCO gain. A digital FLL/PLL of the present invention includes: a comparator for comparing a channel signal to a loopback signal having an oscillation frequency to generate a signal error; a digital loop filter for generating a control voltage that determines the oscillation frequency, on the basis of the signal error; a VCO for controlling an oscillation frequency on the basis of the control voltage; a loopback path through which the oscillation frequency generated by the VCO is outputted as the loopback signal to the comparator; and a control section for monitoring the signal error, and controlling the digital loop filter such that the oscillation frequency of the VCO becomes a stationary state, when detecting that the signal error meets a predetermined condition after the channel signal is switched.
    • 提供了一种数字FLL / PLL,其能够以高速将VCO的振荡频率收敛到期望的频率,而不设置对应于每个VCO增益的阻尼因子。 本发明的数字FLL / PLL包括:比较器,用于将信道信号与具有振荡频率的环回信号进行比较以产生信号误差; 数字环路滤波器,用于基于信号误差产生确定振荡频率的控制电压; 用于基于所述控制电压来控制振荡频率的VCO; 由VCO产生的振荡频率作为环回信号输出到比较器的环回路径; 以及用于监视信号误差的控制部分,并且当在信道信号被切换之后检测到信号误差满足预定条件时,控制数字环路滤波器使得VCO的振荡频率变为静止状态。
    • 5. 发明授权
    • Transmitter including polar modulation circuit
    • 发射机包括极性调制电路
    • US08477870B2
    • 2013-07-02
    • US13380947
    • 2010-04-09
    • Masakatsu Maeda
    • Masakatsu Maeda
    • H04L27/00
    • H03F1/0205H03F3/24H03F2200/324H03F2200/336
    • Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art. The polar modulation circuit includes: a first calculator for performing an exclusive OR logical operation between the amplitude component before and after being inputted to the first processing section; a second calculator for performing an exclusive OR logical operation between the phase component before and after being inputted to the second processing section; and a delay fluctuation detection/compensation section for obtaining a delay time of the amplitude component based on an amount of output accumulation of the first calculator; obtaining a delay time of the phase component based on an amount of output accumulation of the second calculator; detecting an amount of delay fluctuation by using the delay times; and adjusting timings of the amplitude component and the phase component.
    • 提供了一种发射器,其包括极限调制电路,其比常规技术更准确地调节幅度分量和相位分量之间的定时滞后。 极坐标调制电路包括:第一计算器,用于在输入到第一处理部分之前和之后的幅度分量之间执行异或逻辑运算; 第二计算器,用于在输入到第二处理部分之前和之后的相位分量之间执行异或逻辑运算; 以及延迟波动检测/补偿部分,用于基于第一计算器的输出累积量来获得振幅分量的延迟时间; 基于第二计算器的输出累积量获得相位分量的延迟时间; 通过使用延迟时间检测延迟波动量; 并调整振幅分量和相位分量的定时。
    • 6. 发明申请
    • TRANSMITTER INCLUDING POLAR MODULATION CIRCUIT
    • 发射机,包括极性调制电路
    • US20120105111A1
    • 2012-05-03
    • US13380947
    • 2010-04-09
    • Masakatsu Maeda
    • Masakatsu Maeda
    • H03C1/00H03B21/00
    • H03F1/0205H03F3/24H03F2200/324H03F2200/336
    • Provided is a transmitter including a polar modulation circuit which adjusts a timing lag between an amplitude component and a phase component more accurately than a conventional art. The polar modulation circuit includes: an extraction section for extracting an amplitude component and a phase component from an input signal; a first processing section for performing a first signal process on the amplitude component; a second processing section for performing a second signal processing on the phase component; an amplifier for synthesizing an output of the first processing section and an output of the second processing section and amplifying the synthesized outputs; a first calculator for performing an exclusive OR logical operation between the amplitude component before being inputted to the first processing section and the amplitude component after having been inputted to the first processing section; a first accumulation section for accumulating outputs of the first calculator; a second calculator for performing an exclusive OR logical operation between the phase component before being inputted to the second processing section and the phase component after having been inputted to the second processing section; a second accumulation section for accumulating outputs of the second calculator; and a delay fluctuation detection/compensation section for obtaining a delay time of the amplitude component based on an amount of accumulation of the first accumulation section; obtaining a delay time of the phase component based on an amount of accumulation of the second accumulation section; detecting an amount of delay fluctuation by using the delay times; and adjusting timings of the amplitude component and the phase component.
    • 提供了一种发射器,其包括极限调制电路,其比常规技术更准确地调节幅度分量和相位分量之间的定时滞后。 极坐标调制电路包括:提取部分,用于从输入信号中提取振幅分量和相位分量; 第一处理部分,用于对振幅分量执行第一信号处理; 第二处理部,对相位成分进行第二信号处理; 用于合成第一处理部分的输出和第二处理部分的输出并放大合成输出的放大器; 第一计算器,用于在输入到第一处理部分之前的幅度分量和已经被输入到第一处理部分之后的幅度分量之间执行异或逻辑运算; 第一累积部分,用于累积第一计算器的输出; 第二计算器,用于在输入到第二处理部分之前的相位分量和被输入到第二处理部分之后的相位分量之间执行异或逻辑运算; 第二累积部分,用于累积第二计算器的输出; 以及延迟波动检测/补偿部分,用于基于第一累积部分的累积量获得振幅分量的延迟时间; 基于第二累积部分的累积量获得相位分量的延迟时间; 通过使用延迟时间检测延迟波动量; 并调整振幅分量和相位分量的定时。
    • 9. 发明授权
    • Semiconductor apparatus and radio circuit apparatus using the same
    • 半导体装置及其使用的无线电电路装置
    • US07974333B2
    • 2011-07-05
    • US11994542
    • 2006-06-27
    • Masakatsu Maeda
    • Masakatsu Maeda
    • H04B1/38
    • H04B1/30H03L7/183
    • A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size.
    • 半导体装置包括输出预定频率的信号的信号源7,接收信号源的输出信号并且能够将输出信号切换到两个或更多个分频比的分频器15,Δ-Σ调制器 16,其控制分频器的分频比,以及带通滤波器17,其接收分频器的输出。 分频器的输入信号的频率除以由Δ-Σ调制器控制的分频比,并且由Δ-Σ调制器产生的分频器的输出中出现的量化噪声被带通滤波器衰减。 半导体装置可以容易地将由单个信号源输出的信号转换为预定频率的信号,并且使用具有减小的芯片尺寸的简单配置来提供预定频率的多个信号。