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1. 发明授权

US06529522B1 Communication apparatus with digital interface 失效
标题翻译：具有数字接口的通信设备
公开(公告)号：US06529522B1
公开(公告)日：2003-03-04
申请号：US09041122
申请日：1998-03-12
申请人： Masamichi Ito , Koji Takahashi , Hiroki Yamashita
发明人： Masamichi Ito , Koji Takahashi , Hiroki Yamashita
IPC分类号： H04L1246
CPC分类号： H04N1/00278 , G06F13/4027 , H04N1/00236 , H04N1/00241 , H04N2201/0015 , H04N2201/0044 , H04N2201/0049 , H04N2201/0053 , H04N2201/0055 , H04N2201/0081 , H04N2201/0084
摘要： The communication apparatus is equipped with a first communication interface for executing communication based on a first communication method, and a second communication interface for executing communication based on a second communication method different from the first communication method. The communication apparatus sets ID information for identifying device executing communication by the first communication method, for device which executes communication with the second communication interface. In this manner plural device supporting different communication methods can be recognized as device belonging to a same communication system.
摘要翻译：通信装置配备有用于基于第一通信方法执行通信的第一通信接口和用于基于与第一通信方法不同的第二通信方法来执行通信的第二通信接口。通信装置设置用于通过第一通信方法识别执行通信的设备的ID信息，用于执行与第二通信接口的通信的设备。以这种方式，支持不同通信方式的多个设备可以被识别为属于同一通信系统的设备。

2. 发明授权

US08993952B2 Transimpedance amplifier, semiconductor device, and optical module to include an adding circuit for adding first and second current variation 有权
标题翻译：互阻放大器，半导体器件和光学模块，包括用于添加第一和第二电流变化的加法电路
公开(公告)号：US08993952B2
公开(公告)日：2015-03-31
申请号：US13546382
申请日：2012-07-11
申请人： Takashi Takemoto , Hiroki Yamashita , Shinji Tsuji
发明人： Takashi Takemoto , Hiroki Yamashita , Shinji Tsuji
IPC分类号： H01J40/14 , H03F3/08 , H03F1/02 , H03F1/08
CPC分类号： H03F3/085 , H03F1/0222 , H03F1/0233 , H03F1/083 , H03F3/087 , H03F2200/372 , H03F2200/504 , H03F2200/78
摘要： An optical module including a transimpedance amplifier capable of realizing a high-speed and high-quality receiving operation is provided. A transimpedance amplifier includes: a pre-amplifier using a single-end current signal as an input and converting the single-end current signal to a single-end voltage signal; an automatic decision threshold control detecting a center electric potential of the single-end voltage signal serving as an output of the pre-amplifier; a post-amplifier differentiating and amplifying the single-end voltage signal of the output of the pre-amplifier; and a power circuit supplying power to the pre-amplifier. Particularly, in accordance with an input voltage signal or an output voltage signal of the pre-amplifier, the power circuit outputs a varied current that flows to a supply terminal of the pre-amplifier and a varied current having a phase opposite to that of the varied current. Thus, the power supply current change is cancelled out.
摘要翻译：提供一种包括能够实现高速和高质量接收操作的跨阻放大器的光学模块。跨阻放大器包括：使用单端电流信号作为输入并将单端电流信号转换为单端电压信号的前置放大器; 检测用作前置放大器的输出的单端电压信号的中心电位的自动判定阈值控制; 后置放大器对前置放大器输出的单端电压信号进行差分放大; 以及向前置放大器供电的电源电路。特别地，根据前置放大器的输入电压信号或输出电压信号，电源电路输出流向前置放大器的电源端子的变化的电流和与变化的电流。因此，电源电流变化被消除。

3. 发明授权

US08871602B2 Method for manufacturing molecular memory device 有权
标题翻译：制造分子记忆装置的方法
公开(公告)号：US08871602B2
公开(公告)日：2014-10-28
申请号：US13422488
申请日：2012-03-16
申请人： Hiroki Yamashita
发明人： Hiroki Yamashita
IPC分类号： H01L21/02 , H01L27/28 , G11C13/00 , H01L51/05
CPC分类号： G11C13/0016 , G11C13/0014 , H01L27/285 , H01L51/0003 , H01L51/0021 , H01L51/0591 , H01L51/0595
摘要： According to one embodiment, a method for manufacturing a molecular memory device includes: forming a first wiring layer including a plurality of first wirings extending in a first direction; forming a sacrificial film on the first wiring layer; forming a plurality of core members on the first wiring layer, the core member extending in a second direction crossing the first direction and being formed from an insulating material different from the sacrificial film; forming a second wiring on a side surface of the core member; removing a portion of the sacrificial film located immediately below the second wiring; embedding a polymer; and embedding an insulating. The embedding a polymer includes embedding a polymer serving as a memory material between the first wiring and the second wiring. The embedding an insulating member includes embedding an insulating member in a space between the second wirings between the core members.
摘要翻译：根据一个实施例，一种用于制造分子存储器件的方法包括：形成包括沿第一方向延伸的多个第一布线的第一布线层; 在第一布线层上形成牺牲膜; 在所述第一布线层上形成多个芯构件，所述芯构件沿与所述第一方向交叉的第二方向延伸并且由与所述牺牲膜不同的绝缘材料形成; 在所述芯构件的侧表面上形成第二布线; 去除位于第二布线正下方的牺牲膜的一部分; 嵌入聚合物; 并嵌入绝缘。嵌入聚合物包括在第一布线和第二布线之间嵌入用作存储材料的聚合物。嵌入绝缘构件包括将绝缘构件嵌入在芯构件之间的第二布线之间的空间中。

4. 发明授权

US08503595B2 Data judgment/phase comparison circuit 失效
标题翻译：数据判断/相位比较电路
公开(公告)号：US08503595B2
公开(公告)日：2013-08-06
申请号：US13255902
申请日：2009-09-29
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H03K5/26
CPC分类号： H03K5/26 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/033
摘要： The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC.
摘要翻译：本发明涉及一种包括时钟产生电路的时钟发生电路和信号再现电路，更具体地说，本发明提供一种能够通过单相时钟执行数据判断和相位比较两者的数据判断/相位比较电路并且提供包括数据判断/相位比较电路的CDR（时钟数据恢复）电路。相同的数据和时钟输入到具有正确判断数据所需的不同数据确定周期（建立/保持时间）的两个数据判断单元C_GOOD和C_BAD，并且具有较短的所需数据确定的数据判断单元C_GOOD的输出将周期作为数据判断/相位比较电路的数据输出。当两个数据判断单元的输出彼此不同时，输出表示时钟相位太早的信号Early，或指示时钟相位太迟的信号Late。根据通过组合符号和先前和之后的符号获得的总共三个符号的数据输出之间的关系，选择Early或Late由判决逻辑EL_LOGIC输出。

5. 发明授权

US08493103B2 Output driver circuit 有权
标题翻译：输出驱动电路
公开(公告)号：US08493103B2
公开(公告)日：2013-07-23
申请号：US12987092
申请日：2011-01-08
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K5/151 , H03K19/01721 , H04L25/0272 , H04L25/0278 , H04L25/0282 , H04L25/0286 , H04L25/03878
摘要： Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively. VSG_BK decides a voltage level at TXP, TXN, in the stationary state, keeping TXP, TXN as terminal nodes at impedance Z0, respectively.
摘要翻译：公开了除了传输速度的提高之外，还能够实现功率消耗的降低和/或传输波形质量的提高。输出驱动电路例如具有用于通过电压驱动正负输出节点（TXP，TXN）的电压信号生成电路块VSG_BK，用于产生脉冲信号的脉冲信号生成电路PGEN1，PGEN2 数据输入信号DIN_P，DIN_N和电流信号产生电路块ISG_BKp1，ISG_BKn1的转换，用于在脉冲信号的脉冲宽度的持续时间内通过电流驱动TXP，TXN。电流信号发生电路块分别对发生在阻抗Z0上的寄生电容器Cp1，Cp2进行充电，分别执行对TXP，TXN发生的寄生电容器Cp1，Cp2的高速充电。在固定状态下，VSG_BK决定TXP，TXN的电压电平，分别将TXP，TXN作为终端节点保持在阻抗Z0。

6. 发明申请

US20120187980A1 TRANSMITTER CIRCUIT 失效
标题翻译：发射机电路
公开(公告)号：US20120187980A1
公开(公告)日：2012-07-26
申请号：US13358324
申请日：2012-01-25
申请人： Hiroaki KURAHASHI , Tomofumi Hokari , Takashi Muto , Goichi Ono , Hiroki Yamashita
发明人： Hiroaki KURAHASHI , Tomofumi Hokari , Takashi Muto , Goichi Ono , Hiroki Yamashita
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018514
摘要： A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.
摘要翻译：一种发射机电路，其中驱动电路包括用于偏压施加的MOS晶体管，其中驱动电流流动，共源共栅连接到MOS晶体管，用于由传输数据信号的电压值控制的差分信号输入，由电压值偏置电压和驱动电路包括用于偏置电压施加的MOS晶体管，其中驱动电流流动，共源共栅连接到用于差分信号输入的MOS晶体管，该MOS晶体管由通过发送的数据信号获得的信号的电压值控制，连接到负载部分，并由偏置电压的电压值控制。

7. 发明申请

US20110316632A1 OPTICAL COMMUNICATION DEVICE 有权
标题翻译：光通信设备
公开(公告)号：US20110316632A1
公开(公告)日：2011-12-29
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/16 , H03F1/22 , H03G3/20
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

8. 发明申请

US20110001588A1 WAVEFORM EQUALIZATION CIRCUIT WITH PULSE WIDTH MODULATION 有权
标题翻译：波形宽度调制的波形均衡电路
公开(公告)号：US20110001588A1
公开(公告)日：2011-01-06
申请号：US12826648
申请日：2010-06-29
申请人： Fumio YUKI , Hiroki Yamashita , Koji Fukuda
发明人： Fumio YUKI , Hiroki Yamashita , Koji Fukuda
IPC分类号： H04B3/04
CPC分类号： H04B3/04
摘要： There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width. With the use of such a waveform equalization scheme as above, it is possible to attain reduction in power consumption due to simplification in circuit configuration, and further, use of CMOS circuits will enable power consumption to be held back to a low level.
摘要翻译：提供具有脉冲宽度调制的波形均衡电路，其包括脉冲宽度调整电平生成电路PWCLC1a，PWCLC2a，用于分别基于先前的输入数据单元Din_P，Din_N产生脉冲宽度调整电平VCNT，脉冲用于调整根据VCNT的脉冲宽度的宽度调整电路PWCC1a，PWCC2a以及用于整形来自每个脉冲宽度调节电路的输出信号的波形的波形整形电路WAC。脉冲宽度调整电路具有根据前述各输入数据单元的连续比特数进行控制的驱动功率，并且改变每个输出数据单元Do1_P，Do1_N的转换时间，从而调整脉冲宽度。通过使用如上所述的这种波形均衡方案，由于电路结构的简化，可以实现功耗的降低，此外，使用CMOS电路将能够将功耗抑制到低水平。

9. 发明授权

US07764090B2 Semiconductor device having transmitter/receiver circuit between circuit blocks 失效
标题翻译：在电路块之间具有发射机/接收机电路的半导体器件
公开(公告)号：US07764090B2
公开(公告)日：2010-07-27
申请号：US12105586
申请日：2008-04-18
申请人： Hiroki Yamashita , Ryo Nemoto
发明人： Hiroki Yamashita , Ryo Nemoto
IPC分类号： H03K3/00
CPC分类号： H03K19/018557
摘要： A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.
摘要翻译：接收器电路包括分别连接到一对第一和第二接收端子以接收互补电流信号的第一和第二恒定电流源，连接到其源极的第一NMOS晶体管与第一接收端子和第一恒定电流源连接，其漏极经由第一输出端子和第一负载装置到第一电源，以及第二NMOS晶体管，其源极连接到第二接收端子和第二恒流源，并在其漏极处连接到第一电源经由第二输出端子和第二负载装置。

10. 发明申请

US20090296851A1 Pre-emphasis circuit 有权
标题翻译：预加重电路
公开(公告)号：US20090296851A1
公开(公告)日：2009-12-03
申请号：US12453981
申请日：2009-05-28
申请人： Goichi Ono , Hiroki Yamashita
发明人： Goichi Ono , Hiroki Yamashita
IPC分类号： H04L27/00
CPC分类号： H04L25/0272
摘要： A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.
摘要翻译：提供了可以以低成本提高数据传输的通信质量的预加重电路。电流开关电路，电流加法器电路和转移检测电路设置在数据传输系统的发射机中。转移检测电路检测作为差分对的发送数据信号的转变。电流开关电路接收发送数据信号，根据发送数据信号传送驱动电流，并输出作为差分对的输出数据信号。电流加法器电路接收来自转换检测电路的检测信号，并根据检测信号将驱动电流加到负载电阻上。通过这种方式，将转换强调的输出数据信号输入到传输线。

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