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1. 发明申请

US20100166289A1 FEATURE-QUANTITY EXTRACTING METHOD, DESIGNED-CIRCUIT-PATTERN VERIFYING METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：特征提取方法，设计电路图形验证方法和计算机程序产品
公开(公告)号：US20100166289A1
公开(公告)日：2010-07-01
申请号：US12646677
申请日：2009-12-23
申请人： Masaki SATAKE , Masafumi Asano , Satoshi Tanaka , Taiga Uno
发明人： Masaki SATAKE , Masafumi Asano , Satoshi Tanaka , Taiga Uno
IPC分类号： G06K9/46 , G06T7/00
CPC分类号： G03F1/44 , G03F7/705
摘要： Feature-quantity extraction parameters used by feature-quantity extraction functions for calculating feature quantities used as explanatory variables of a resist model for predicting a resist image are set. The feature-quantity extraction functions, for which the feature-quantity extraction parameters are set, are caused to act on optical images of a pattern of a photomask to calculate feature quantities from the optical images.
摘要翻译：设置用于计算用作预测抗蚀剂图像的抗蚀剂模型的解释变量的特征量的特征量提取函数所使用的特征量提取参数。使特征量提取参数被设置的特征量提取功能作用于光掩模图案的光学图像，以计算来自光学图像的特征量。

2. 发明申请

US20080134131A1 Simulation model making method 审中-公开
标题翻译：仿真模型制作方法
公开(公告)号：US20080134131A1
公开(公告)日：2008-06-05
申请号：US11976025
申请日：2007-10-19
申请人： Masafumi Asano , Masaki Satake , Satoshi Tanaka
发明人： Masafumi Asano , Masaki Satake , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70425 , G03F7/70491 , G03F7/705 , G03F7/70616
摘要： A method of making a simulation model, includes specifying a feature factor which characterizes a pattern layout of a mask pattern, specifying a control factor which affects a dimension of a resist pattern to be formed on a substrate by means of a lithography process using the mask pattern, determining a predicted dimension of the resist pattern to be formed on the substrate by means of the lithography process using the mask pattern through the use of a model based on the feature and control factors, obtaining an actual dimension of the resist pattern actually formed on the substrate by means of the lithography process using the mask pattern, and setting the feature and control factors and the predicted dimension as input layers and setting the actual dimension as an output layer to construct a neural network.
摘要翻译：一种制作仿真模型的方法包括指定表征掩模图案的图案布局的特征因子，通过使用掩模的光刻工艺指定影响待形成在抗蚀剂图案的尺寸的控制因素通过使用基于特征和控制因子的模型通过使用掩模图案的光刻处理来确定要在基板上形成的抗蚀剂图案的预测尺寸，获得实际形成的抗蚀剂图案的实际尺寸通过使用掩模图案的光刻工艺在衬底上，并将特征和控制因子和预测尺寸设置为输入层，并将实际尺寸设置为输出层以构建神经网络。

3. 发明授权

US07855047B2 Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device 有权
公开(公告)号：US07855047B2
公开(公告)日：2010-12-21
申请号：US12654292
申请日：2009-12-16
申请人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
发明人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
IPC分类号： H01L21/00 , G03F1/00 , G03C5/00
CPC分类号： G03F7/70466 , G03F1/44 , G03F1/70 , G03F7/70625
摘要： A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.

4. 发明授权

US07175943B2 Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device 失效
公开(公告)号：US07175943B2
公开(公告)日：2007-02-13
申请号：US10725571
申请日：2003-12-03
申请人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
发明人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
IPC分类号： G01F9/00
CPC分类号： G03F7/70466 , G03F1/44 , G03F1/70 , G03F7/70625
摘要： A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.

5. 发明授权

US07396621B2 Exposure control method and method of manufacturing a semiconductor device 失效
标题翻译：曝光控制方法及制造半导体器件的方法
公开(公告)号：US07396621B2
公开(公告)日：2008-07-08
申请号：US11819375
申请日：2007-06-27
申请人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
发明人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
IPC分类号： G03F7/16 , G03F7/20 , G03F7/38 , G03F1/14
CPC分类号： G03F1/44
摘要： A method of manufacturing a semiconductor device includes preparing a projection exposure apparatus and a photomask, the photomask having a transparent substrate and a light shield film arranged in patterns to be transferred to a resist film on a wafer. The patterns include a circuit mask pattern, and first and second mark mask patterns having dimensions which change in accordance with exposure of the resist film. The method further includes forming first and second exposure monitor marks by causing phasing differences of 180 degrees and zero degrees, respectively, of light passing through the corresponding first and second mark mask patterns; measuring the first and second exposure monitor marks; calculating first and second effective exposures based on measured dimensions of the first and second exposure monitor marks; comparing variations of the first and second effective exposures; and changing at least one of a deposit condition of a front-end film formed under the resist film or a resist film coating condition if a variation of the first effective exposure differs from a variation of the second effective exposure.
摘要翻译：制造半导体器件的方法包括制备投影曝光设备和光掩模，所述光掩模具有透明基板和以图案排列的光屏蔽膜，以转印到晶片上的抗蚀剂膜。图案包括电路掩模图案，以及具有根据抗蚀剂膜的曝光而变化的尺寸的第一和第二标记掩模图案。该方法还包括通过分别通过相应的第一和第二标记掩模图案的光180度和零度的相位差来形成第一和第二曝光监视标记; 测量第一和第二曝光监视标记; 基于第一和第二曝光监视标记的测量尺寸来计算第一和第二有效曝光; 比较第一和第二有效曝光的变化; 以及如果第一有效曝光的变化与第二有效曝光的变化不同，则改变形成在抗蚀剂膜下方的前端膜的沉积条件或抗蚀剂膜涂覆条件中的至少一个。

6. 发明申请

US20100112485A1 Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device 有权
标题翻译：掩模版，掩模版集合的设计方法，曝光监视方法，掩模版集合的检查方法以及半导体器件的制造方法
公开(公告)号：US20100112485A1
公开(公告)日：2010-05-06
申请号：US12654292
申请日：2009-12-16
申请人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
发明人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F1/44 , G03F1/70 , G03F7/70625
摘要： A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.
摘要翻译：标线组包括具有电路图案的第一光掩模，该电路图案设置有彼此相邻设置的夹着第一不透明部分的第一和第二开口以及邻近电路图案设置的监视标记; 以及第二光掩模，其具有装饰图案，其具有覆盖所述电路图案占据的区域中的所述第一不透明部分的第二不透明部分和连接到所述第一不透明部分的一端的延伸部分，并且当所述第二光掩模为与通过第一光掩模在衬底上描绘的图案对准。

7. 发明申请

US20070259280A1 Photomask, exposure control method and method of manufacturing a semiconductor device 失效
标题翻译：光掩模，曝光控制方法和制造半导体器件的方法
公开(公告)号：US20070259280A1
公开(公告)日：2007-11-08
申请号：US11819375
申请日：2007-06-27
申请人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
发明人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
IPC分类号： G03F7/20 , G03F1/00 , G03C5/00 , G03F7/40 , G03F7/38
CPC分类号： G03F1/44
摘要： A photomask transferring a light shield film pattern formed on a transparent substrate by a projection exposure apparatus, comprising a circuit pattern for transferring a predetermined pattern to a resist film, and an exposure monitor mark, the exposure monitor mark being formed in a manner that blocks having a predetermined width p, which are not resolved by the projection exposure apparatus, are intermittently or continuously arrayed along one direction, light shield and transmission portions are arrayed along one direction in each of the blocks, the blocks are arrayed so that a dimension ratio of the light shield and transmission portions of the blocks simply changes and the phase difference of exposure light passing through adjacent light transmission portions is approximately 180°.
摘要翻译：一种光掩模，其通过投影曝光装置将形成在透明基板上的遮光膜图案转印，所述投影曝光装置包括用于将预定图案转印到抗蚀剂膜的电路图案，以及曝光监视标记，所述曝光监视标记以块具有未被投影曝光装置解析的预定宽度p沿着一个方向间歇地或连续地排列，在每个块中沿着一个方向排列有光屏蔽和透射部分，块被排列成使得尺寸比的光屏蔽和透射部分简单地改变，并且穿过相邻光传输部分的曝光光的相位差大约为180°。

8. 发明申请

US20050030502A1 Photomask, exposure control method and method of manufacturing a semiconductor device 审中-公开
标题翻译：光掩模，曝光控制方法和制造半导体器件的方法
公开(公告)号：US20050030502A1
公开(公告)日：2005-02-10
申请号：US10874192
申请日：2004-06-24
申请人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
发明人： Tadahito Fujisawa , Soichi Inoue , Satoshi Tanaka , Masafumi Asano
IPC分类号： G03B27/42 , G03F1/26 , G03F1/38 , G03F1/44 , G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： G03F1/44
摘要： A photomask transferring a light shield film pattern formed on a transparent substrate by a projection exposure apparatus, comprising a circuit pattern for transferring a predetermined pattern to a resist film, and an exposure monitor mark, the exposure monitor mark being formed in a manner that blocks having a predetermined width p, which are not resolved by the projection exposure apparatus, are intermittently or continuously arrayed along one direction, light shield and transmission portions are arrayed along one direction in each of the blocks, the blocks are arrayed so that a dimension ratio of the light shield and transmission portions of the blocks simply changes and the phase difference of exposure light passing through adjacent light transmission portions is approximately 180°.
摘要翻译：一种光掩模，其通过投影曝光装置将形成在透明基板上的遮光膜图案转印，所述投影曝光装置包括用于将预定图案转印到抗蚀剂膜的电路图案，以及曝光监视标记，所述曝光监视标记以块具有未被投影曝光装置解析的预定宽度p沿着一个方向间歇地或连续地排列，在每个块中沿着一个方向排列有光屏蔽和透射部分，块被排列成使得尺寸比的光屏蔽和透射部分简单地改变，并且穿过相邻光传输部分的曝光光的相位差大约为180°。

9. 发明授权

US07655369B2 Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device 失效
公开(公告)号：US07655369B2
公开(公告)日：2010-02-02
申请号：US11646480
申请日：2006-12-28
申请人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
发明人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
IPC分类号： G03C5/00 , G03F9/00 , G03F1/00
CPC分类号： G03F7/70466 , G03F1/44 , G03F1/70 , G03F7/70625
摘要： A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.

10. 发明申请

US20070105028A1 Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device 失效
标题翻译：掩模版，掩模版集合的设计方法，曝光监视方法，掩模版集合的检查方法以及半导体器件的制造方法
公开(公告)号：US20070105028A1
公开(公告)日：2007-05-10
申请号：US11646480
申请日：2006-12-28
申请人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
发明人： Masafumi Asano , Tadahito Fujisawa , Satoshi Tanaka
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F7/70466 , G03F1/44 , G03F1/70 , G03F7/70625
摘要： A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.
摘要翻译：标线组包括具有电路图案的第一光掩模，该电路图案设置有彼此相邻设置的夹着第一不透明部分的第一和第二开口以及邻近电路图案设置的监视标记; 以及第二光掩模，其具有装饰图案，其具有覆盖所述电路图案占据的区域中的所述第一不透明部分的第二不透明部分和连接到所述第一不透明部分的一端的延伸部分，并且当所述第二光掩模为与通过第一光掩模在衬底上描绘的图案对准。

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