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1. 发明授权

US06054371A Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board 失效
标题翻译：通过将基板可拆卸地安装到保持板来制造半导体器件的方法
公开(公告)号：US06054371A
公开(公告)日：2000-04-25
申请号：US162155
申请日：1998-09-29
申请人： Masakatsu Tsuchiaki , Yasushi Nakasaki , Akira Nishiyama , Yukihito Oowaki , Hirotaka Nishino
发明人： Masakatsu Tsuchiaki , Yasushi Nakasaki , Akira Nishiyama , Yukihito Oowaki , Hirotaka Nishino
IPC分类号： H01L21/762 , H01L21/02 , H01L21/68 , H01L25/04 , H01L25/18 , H01L27/108 , H01L27/12 , H01L21/30 , H01L21/00 , H01L21/44 , H01L21/46 , H01L21/84
CPC分类号： H01L21/6835 , H01L2221/68313 , H01L27/10897 , H01L2924/0002 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： Disclosed is a method of manufacturing a semiconductor device, comprising the step of detachably mounting a plurality of semiconductor substrates to a first holder board so as to form a complex semiconductor substrate, and the step of subjecting the plural semiconductor substrates included in the complex semiconductor substrates to common steps of manufacturing a semiconductor device. At least one of the plural semiconductor substrates is mounted to a second holder board. The particular semiconductor substrate is detached from the second holder board and, then, mounted to the first holder board. Alternatively, at least one of the plural semiconductor substrates is detached from the first holder board and, then, mounted to a third holder board differing in size from the first holder board.
摘要翻译：公开了一种制造半导体器件的方法，包括以下步骤：将多个半导体衬底可拆卸地安装到第一保持器板以形成复合半导体衬底;以及对包含在复合半导体衬底中的多个半导体衬底进行处理的步骤涉及制造半导体器件的常规步骤。多个半导体衬底中的至少一个安装到第二保持器板。特定的半导体衬底从第二保持器板分离，然后安装到第一保持器板。或者，多个半导体衬底中的至少一个从第一保持器板分离，然后安装到尺寸与第一保持器板不同的第三保持器板。

2. 发明授权

US07303965B2 MIS transistor and method for producing same 失效
标题翻译： MIS晶体管及其制造方法
公开(公告)号：US07303965B2
公开(公告)日：2007-12-04
申请号：US09879208
申请日：2001-06-13
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L21/33 , H01L21/3205 , H01L31/00
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

3. 发明授权

US06278165B1 MIS transistor having a large driving current and method for producing the same 有权
标题翻译：具有大驱动电流的MIS晶体管及其制造方法
公开(公告)号：US06278165B1
公开(公告)日：2001-08-21
申请号：US09340149
申请日：1999-06-28
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

4. 发明授权

US06690047B2 MIS transistor having a large driving current and method for producing the same 失效
标题翻译：具有大驱动电流的MIS晶体管及其制造方法
公开(公告)号：US06690047B2
公开(公告)日：2004-02-10
申请号：US10132175
申请日：2002-04-26
申请人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
发明人： Yukihito Oowaki , Mizuki Ono , Mitsuhiro Noguchi , Daisaburo Takashima , Akira Nishiyama
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66621 , H01L29/78
摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.
摘要翻译：在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜的高介电膜和栅电极。或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

5. 发明授权

US08008147B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08008147B2
公开(公告)日：2011-08-30
申请号：US12320278
申请日：2009-01-22
申请人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
发明人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/28194 , H01L21/28202 , H01L29/4933 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
摘要翻译：可以尽可能地防止器件特性的劣化。半导体器件包括：半导体衬底; 栅极绝缘膜，设置在所述半导体衬底的上方并且含有金属，氧和添加元素; 设置在所述栅极绝缘膜上方的栅电极; 以及设置在栅电极两侧的半导体衬底中的源/漏区。添加元素是选自浓度为0.003原子％以上且3原子％以下的第5,6,15和16族元素中的至少一种元素。

6. 发明授权

US07834408B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07834408B2
公开(公告)日：2010-11-16
申请号：US12320279
申请日：2009-01-22
申请人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
发明人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28194 , H01L21/28202 , H01L29/4933 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
摘要翻译：可以尽可能地防止器件特性的劣化。半导体器件包括：半导体衬底; 栅极绝缘膜，设置在所述半导体衬底的上方并且含有金属，氧和添加元素; 设置在所述栅极绝缘膜上方的栅电极; 以及设置在栅电极两侧的半导体衬底中的源/漏区。添加元素是选自浓度为0.003原子％以上且3原子％以下的第5,6,15和16族元素中的至少一种元素。

7. 发明授权

US08154072B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08154072B2
公开(公告)日：2012-04-10
申请号：US12403493
申请日：2009-03-13
申请人： Masahiro Koike , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
发明人： Masahiro Koike , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/513
摘要： A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：在半导体层中形成为彼此间隔一定距离的源区和漏区; 形成在位于源极区域和漏极区域之间的半导体层上的第一绝缘膜，所述第一绝缘膜包括形成在所述第一绝缘层上并具有比所述第一绝缘层高的介电常数的第一绝缘层和第二绝缘层所述第二绝缘层具有进行孔捕获和释放的第一部位，所述第一部位通过将不同于基材的元素添加到所述第二绝缘膜而形成，所述第一部位位于比所述第二绝缘膜的费米能级更低的水平形成半导体层的材料; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

8. 发明申请

US20090134479A1 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US20090134479A1
公开(公告)日：2009-05-28
申请号：US12320280
申请日：2009-01-22
申请人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
发明人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
IPC分类号： H01L29/78
CPC分类号： H01L27/11521 , H01L21/28194 , H01L21/28202 , H01L29/4933 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

9. 发明申请

US20100052035A1 NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100052035A1
公开(公告)日：2010-03-04
申请号：US12403493
申请日：2009-03-13
申请人： Masahiro KOIKE , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
发明人： Masahiro KOIKE , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/513
摘要： A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：在半导体层中形成为彼此间隔一定距离的源区和漏区; 形成在位于源极区域和漏极区域之间的半导体层上的第一绝缘膜，所述第一绝缘膜包括形成在所述第一绝缘层上并具有比所述第一绝缘层高的介电常数的第一绝缘层和第二绝缘层所述第二绝缘层具有进行孔捕获和释放的第一部位，所述第一部位通过将不同于基材的元素添加到所述第二绝缘膜而形成，所述第一部位位于比所述第二绝缘膜的费米能级更低的水平形成半导体层的材料; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

10. 发明申请

US20090166767A1 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US20090166767A1
公开(公告)日：2009-07-02
申请号：US12320279
申请日：2009-01-22
申请人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
发明人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
IPC分类号： H01L29/78
CPC分类号： H01L27/11521 , H01L21/28194 , H01L21/28202 , H01L29/4933 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

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