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1. 发明授权

US5280453A Semiconductor memory device with noise reduction system 失效
标题翻译：具有降噪系统的半导体存储器件
公开(公告)号：US5280453A
公开(公告)日：1994-01-18
申请号：US705341
申请日：1991-05-24
申请人： Masahumi Miyawaki , Tamihiro Ishimura
发明人： Masahumi Miyawaki , Tamihiro Ishimura
IPC分类号： G11C11/4091 , G11C7/02
CPC分类号： G11C11/4091
摘要： An integrated circuit semiconductor memory device includes a memory array having memory cells. A sensing circuit is coupled to the memory cells through one of first and second bit lines. A first conductive line is for applying a first voltage potential to the sensing circuit, and a second conductive line is for applying a second voltage potential to the sensing circuit. A first field effect transistor is provided having first, second electrodes connected to the first conductive line, and a gate electrode connected to the second conductive line. The sensing circuit has a second field effect transistor and a third field effect transistor of an opposite channel type to the second field effect transistor. The first, second and gate electrodes of the first field effect transistor are formed substantially simultaneously with the first, second and gate electrodes of one of the second and third field effect transistors during manufacture of the integrated circuit semiconductor memory device. Also, the first conductive line is formed substantially simultaneously with the second conductive line during manufacture of the integrated circuit semiconductor memory device.
摘要翻译：集成电路半导体存储器件包括具有存储单元的存储器阵列。感测电路通过第一和第二位线之一耦合到存储器单元。第一导线用于向感测电路施加第一电压电位，第二导线用于向感测电路施加第二电压电位。提供第一场效应晶体管，其具有连接到第一导线的第一，第二电极和连接到第二导线的栅电极。感测电路具有与第二场效应晶体管相反通道类型的第二场效应晶体管和第三场效应晶体管。在集成电路半导体存储器件的制造期间，第一场效应晶体管的第一，第二和第二栅极电极基本上与第二和第三场效应晶体管之一的第一，第二和第二栅极电极形成同时。此外，在集成电路半导体存储器件的制造期间，第一导线基本上与第二导线形成同时形成。

2. 发明授权

US5091886A Dual current data bus clamp circuit of semiconductor memory device 失效
标题翻译：半导体存储器件的双电流数据总线钳位电路
公开(公告)号：US5091886A
公开(公告)日：1992-02-25
申请号：US706206
申请日：1991-05-28
申请人： Masahumi Miyawaki , Tamihiro Ishimura , Yoshio Ohtsuki
发明人： Masahumi Miyawaki , Tamihiro Ishimura , Yoshio Ohtsuki
IPC分类号： G11C11/409 , G11C7/10
CPC分类号： G11C7/1048
摘要： A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

3. 发明授权

US5087957A CMOS memory device with improved sense amplifier biasing 失效
标题翻译：具有改善的读出放大器偏置的CMOS存储器件
公开(公告)号：US5087957A
公开(公告)日：1992-02-11
申请号：US672359
申请日：1991-03-20
申请人： Tamihiro Ishimura , Masahumi Miyawaki , Sanpei Miyamoto , Hidenori Uehara
发明人： Tamihiro Ishimura , Masahumi Miyawaki , Sanpei Miyamoto , Hidenori Uehara
IPC分类号： H01L27/10 , G11C7/06 , G11C11/4074 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108
CPC分类号： H01L27/0921 , G11C11/4074 , G11C11/4091 , G11C7/065 , H01L27/088
摘要： A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.
摘要翻译： CMOS存储器件具有存储单元阵列，形成在第一导电类型的衬底上，用于存储数据。通过连接到存储单元阵列的位线对来输入和输出数据。嵌入在第二导电类型的阱中的第一导电类型的感测放大器放大位线对上的电位差。感测放大器连接到读出放大器驱动信号线并由其驱动。读出放大器驱动信号线还偏置包含读出放大器的阱，从而防止闩锁。

4. 发明授权

US5517444A Semiconductor memory device with resistive power supply connection 失效
标题翻译：具有电阻电源连接的半导体存储器件
公开(公告)号：US5517444A
公开(公告)日：1996-05-14
申请号：US397730
申请日：1995-03-02
申请人： Tamihiro Ishimura , Masahumi Miyawaki , Yoshio Ohtsuki
发明人： Tamihiro Ishimura , Masahumi Miyawaki , Yoshio Ohtsuki
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.
摘要翻译：在具有多个存储单元阵列的半导体存储器件中，其中存储单元连接的一对位线之间的电位差通过响应于公共节点上的读出锁存信号而工作的读出放大器放大，并且存储器单元通过电源线连接到电源，消除或减少由于电源线的电阻引起的不利影响。这是通过将布置在每个存储单元阵列内的电源辅助线和沿着存储单元阵列布置的电源主线通过电阻大于电源主线的电阻的电阻元件而耦合来实现的提供给位于最远的存储单元阵列。或者，每个存储单元阵列中的公共节点经由电阻元件和通过控制信号导通和截止的读出放大器驱动晶体管连接到所述电源主线。或者，通过控制信号导通以将读出放大器连接到电源主线的晶体管根据电源线的电阻具有不同的互导。

5. 发明授权

US5177586A CMOS memory device with improved sense amplifier biasing 失效
标题翻译：具有改进的感测放大器偏置的CMOS存储器件
公开(公告)号：US5177586A
公开(公告)日：1993-01-05
申请号：US818803
申请日：1992-01-09
申请人： Tamihiro Ishimura , Masahumi Miyawaki , Sanpei Miyamoto , Hidenori Uehara
发明人： Tamihiro Ishimura , Masahumi Miyawaki , Sanpei Miyamoto , Hidenori Uehara
IPC分类号： H01L27/10 , G11C7/06 , G11C11/4074 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108
CPC分类号： H01L27/0921 , G11C11/4074 , G11C11/4091 , G11C7/065 , H01L27/088
摘要： A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

6. 发明授权

US5321658A Semiconductor memory device being coupled by auxiliary power lines to a main power line 失效
标题翻译：半导体存储器件通过辅助电源线耦合到主电源线
公开(公告)号：US5321658A
公开(公告)日：1994-06-14
申请号：US702496
申请日：1991-05-20
申请人： Tamihiro Ishimura , Masahumi Miyawaki , Yoshio Ohtsuki
发明人： Tamihiro Ishimura , Masahumi Miyawaki , Yoshio Ohtsuki
IPC分类号： G11C5/14 , G11C11/4074
CPC分类号： G11C11/4074 , G11C5/147
摘要： In semiconductor memory device having a plurality of memory cell arrays in which a potential difference between a pair of bit lines to which memory cells are connected is amplified by a sense amplifier operating responsive to a sense latch signal on a common node, and the memory cells are connected via a power supply line to a power supply, the adverse effects due to the resistance of the power supply line is eliminated or reduced. This is achieved by coupling a power supply auxiliary line disposed within each memory cell array and a power supply main line disposed along the memory cell arrays by means of a resistive element having a resistance larger than the resistance of the power supply main line from the power supply to the memory cell array located farthest. Alternatively, the common node in each memory cell array is connected to said power supply main line via a resistive element and a sense amplifier drive transistor which is turned on and off by a control signal. Still alternatively, the transistors which are turned on by a control signal to connect the sense amplifiers to a power supply main line have a different mutual conductance depending on the resistance of the power supply line.
摘要翻译：在具有多个存储单元阵列的半导体存储器件中，其中存储单元连接的一对位线之间的电位差通过响应于公共节点上的读出锁存信号而工作的读出放大器放大，并且存储器单元通过电源线连接到电源，消除或减少由于电源线的电阻引起的不利影响。这是通过将布置在每个存储单元阵列内的电源辅助线和沿着存储单元阵列布置的电源主线通过电阻大于电源主线的电阻的电阻元件而耦合来实现的提供给位于最远的存储单元阵列。或者，每个存储单元阵列中的公共节点经由电阻元件和通过控制信号导通和截止的读出放大器驱动晶体管连接到所述电源主线。或者，通过控制信号导通以将读出放大器连接到电源主线的晶体管根据电源线的电阻具有不同的互导。

7. 发明授权

US5260904A Data bus clamp circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的数据总线钳位电路
公开(公告)号：US5260904A
公开(公告)日：1993-11-09
申请号：US797954
申请日：1991-11-26
申请人： Masahumi Miyawaki , Tamihiro Ishimura , Yoshio Ohtsuki
发明人： Masahumi Miyawaki , Tamihiro Ishimura , Yoshio Ohtsuki
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1048
摘要： A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.
摘要翻译：用于半导体存储器件的数据总线钳位电路包括用于存储数据的存储单元阵列，行地址解码器，用于解码通过行地址选通信号取入的行地址信号，以选择存储单元的行方向上的存储单元阵列，列地址解码器，用于基于列地址解码器使能信号来选择存储单元阵列的列方向上的存储单元来解码列地址信号，用于发送从存储单元阵列读出的数据的补充数据总线，数据总线用于提升互补数据总线的上拉电路，以及差分放大型读出电路，用于在差分基础上放大互补数据总线上的数据以输出读出数据。数据总线钳位电路包括：第一放电电路，用于在行地址选通信号的有效期间内对互补数据总线上的电荷进行放电;以及第二放电电路，用于放电补充数据总线上的电荷大于在从行地址选通信号的有效周期开始到列地址译码器使能信号变为有效的时间段期间，第一放电电路。

8. 发明授权

US4843258A Drive circuit with a ring oscillator for a semiconductor device 失效
标题翻译：具有用于半导体器件的环形振荡器的驱动电路
公开(公告)号：US4843258A
公开(公告)日：1989-06-27
申请号：US226087
申请日：1988-07-29
申请人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
发明人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G05F3/24 , G11C11/407 , G11C11/413 , H02M3/07 , H03K3/03 , H03K3/354
CPC分类号： G05F3/24 , H03K3/0315 , H03K3/354
摘要： A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.
摘要翻译：用于驱动半导体器件的驱动电路包括用于输出与来自外部电源的输入电压电平相关联的参考电压电平的参考电压电平发生器。提供参考电平，环形振荡器振荡具有预定频率的频率信号。驱动电压电平发生器响应参考电平和频率信号，以产生与频率信号同步地恒定地基本上等于参考电平的驱动电压电平。驱动电压电平发生器将来自外部电源的功率从驱动电平提供给半导体器件，由此驱动半导体负载电路。

9. 发明授权

US5452260A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5452260A
公开(公告)日：1995-09-19
申请号：US215487
申请日：1994-03-21
申请人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
发明人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/10
摘要： A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and first significant information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated to select one memory cell group in the second memory cell block.
摘要翻译：半导体存储器电路响应具有块选择信息的地址信号，第一和第二有效位信息来选择一个存储单元组。首先，对第三存储单元块分别具有各自包含存储单元的存储单元组。首先，第三解码器组分别具有耦合到第一存储器单元块中的一个存储单元组的第一解码器，每个耦合到第二存储单元块中的一个存储单元组的第二解码器，以及每个耦合到一个存储单元组的第三解码器在第三个存储单元块中。第一和第二逻辑电路响应于地址信号的块选择信息分别输出关于第一和第二存储单元块的第一公共块选择信号，以及相对于第二和第三存储器的第二公共块选择信号响应于地址信号的块选择信息的单元块。第三和第四逻辑电路分别响应于第二和第一有效信息，在第一公共块选择信号被输出时，将第一公共解码信号应用于第一和第二解码器组，并将多个第二公共解码信号施加到第二公共解码信号第三解码器组输出第二公共块选择信号。响应于第一和第二公共解码信号，第二解码器组中的第二解码器被激活以选择第二存储器单元块中的一个存储器单元组。

10. 发明授权

US06459327B1 Feedback controlled substrate bias generator 失效
标题翻译：反馈控制衬底偏置发生器
公开(公告)号：US06459327B1
公开(公告)日：2002-10-01
申请号：US07986571
申请日：1992-12-07
申请人： Hitoshi Yamada , Tamihiro Ishimura , Yoshio Ohtsuki
发明人： Hitoshi Yamada , Tamihiro Ishimura , Yoshio Ohtsuki
IPC分类号： H03K301
CPC分类号： H02M3/073 , H03K3/0315 , H03K3/354
摘要： A feedback controlled substrate bias generator having a substrate bias level sensing circuit, a charge pump circuit and an improved oscillator is disclosed. The substrate bias level sensing circuit is coupled to a semiconductor substrate for sensing a bias voltage of the semiconductor substrate and outputting a control signal in response to the sensed bias voltage. The charge pump circuit is coupled to the semiconductor substrate and the substrate bias level sensing circuit for receiving a clock pulse and the control signal and supplying the bias voltage to the semiconductor substrate in response to the received signals. The improved oscillator is coupled to the charge pump circuit for generating the clock pulse. The improved oscillator has a loop circuit having a plurality of serially and circularly coupled inverters each of which has a source terminal applied to voltage from a voltage source, an input terminal for receiving an input signal and an output terminal for outputting an output signal. The improved oscillator further has a plurality of switches each of which has a control terminal, a first terminal coupled to the source terminal of a corresponding inverter of the loop circuit and a second terminal coupled to the voltage source. Each of the switches electrically cuts the first and second terminals when the input signal of the one of the inverters except for the corresponding inverter changes from one level to another.
摘要翻译：公开了一种具有衬底偏置电平检测电路，电荷泵电路和改进的振荡器的反馈控制衬底偏置发生器。衬底偏置电平感测电路耦合到半导体衬底，用于感测半导体衬底的偏置电压，并响应于检测到的偏置电压而输出控制信号。电荷泵电路耦合到半导体衬底和衬底偏置电平检测电路，用于接收时钟脉冲和控制信号，并且响应于接收到的信号将偏置电压提供给半导体衬底。改进的振荡器耦合到电荷泵电路以产生时钟脉冲。改进的振荡器具有环形电路，其具有多个串联和圆形耦合的反相器，每个反相器的源极端子被施加到来自电压源的电压，用于接收输入信号的输入端子和用于输出输出信号的输出端子。改进的振荡器还具有多个开关，每个开关具有控制端子，耦合到环路电路的相应反相器的源极端子的第一端子和耦合到电压源的第二端子。当除了相应的逆变器之外的一个逆变器的输入信号从一个电平变化到另一个电平时，每个开关电切割第一和第二端子。

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