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    • 1. 发明授权
    • Thin film transistor, method for manufacturing same, and liquid crystal display device using same
    • 薄膜晶体管及其制造方法以及使用该薄膜晶体管的液晶显示装置
    • US06888182B2
    • 2005-05-03
    • US10389802
    • 2003-03-18
    • Masahiro MitaniYasumori Fukushima
    • Masahiro MitaniYasumori Fukushima
    • H01L21/336H01L29/786H01L27/148
    • H01L29/78696H01L29/66757H01L29/66772H01L29/78621H01L29/78627H01L2029/7863
    • A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 μm, and the spacing is not less than 3 μm. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.
    • 本发明的薄膜晶体管具备:(i)形成在栅电极下方的多个分割沟道区,(ii)被分割的源极区域和分割的漏极区域,各分割沟道区域夹在其间, 源极区域彼此连接,并且分割的漏极区域彼此连接。 这里,分割的沟道区域被布置成使得分隔沟道区域之间的间隔小于作为一个分割沟道区域的宽度的沟道分割宽度,沟道分割宽度不大于50μm,并且间隔不是 少于3个妈妈。 利用这种布置,可以提供一种薄膜晶体管,其能够通过减小沟道区域的自发热以及能够减小布局面积的增加而降低阈值电压的变化而获得可靠性。
    • 2. 发明授权
    • Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device
    • 用于制造半导体衬底的方法,用于形成半导体衬底的衬底,层叠衬底,半导体衬底和电子器件
    • US08946820B2
    • 2015-02-03
    • US14117158
    • 2012-06-26
    • Masahiro Mitani
    • Masahiro Mitani
    • H01L27/12H01L21/46H01L21/762H01L29/16H01L29/786
    • H01L21/76254H01L27/1266H01L29/16H01L29/78654
    • Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate. A method for manufacturing a SOI substrate (33) in which a plurality of SOI layers (15) are disposed on a base substrate (30) includes the steps of bonding a plurality of SOI wafers (10), in which an oxide film (14), a SOI layer (15), a BOX layer (12), and a Si support substrate (13) having a fragile layer (17) formed by ion irradiation in the inside and being made from a single crystal semiconductor material are stacked sequentially, to a base substrate (30) in such a way that the oxide film (14) is located on the side close to the base substrate (30), applying heat to the plurality of SOI wafers (10) to separate part of the Si support substrate (13) at the fragile layer (17) and transfer the oxide film (14), the SOI layer (15), the BOX layer (12), and a single crystal Si layer (18) which is part of the Si support substrate (13) to the base substrate (30), and subjecting the base substrate (30) to an etch back treatment to expose the BOX layer (12) by etching the transferred single crystal Si layer (18).
    • 在易碎层分离的多个单晶半导体膜中,可以防止膜厚变化,并将其转印到基底。 在基底(30)上设置多个SOI层(15)的SOI衬底(33)的制造方法包括将多个SOI晶片(10)接合的工序,其中,氧化膜(14) ),顺序地层叠具有通过离子照射在内部并由单晶半导体材料制成的脆性层(17)的SOI层(15),BOX层(12)和Si支撑基板(13) 以使得氧化膜(14)位于靠近基底(30)的一侧的方式施加到基底(30),向多个SOI晶片(10)施加热量以分离部分Si 在所述脆弱层(17)处的支撑基板(13),并且将所述氧化物膜(14),所述SOI层(15),所述BOX层(12)和作为所述Si的一部分的单晶Si层(18) 支撑基板(13)到基底基板(30),并且对基底基板(30)进行回蚀处理,以通过蚀刻转移的单个Cr来暴露BOX层(12) ystal Si层(18)。
    • 5. 发明申请
    • METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SUBSTRATE FOR FORMING SEMICONDUCTOR SUBSTRATE, STACKED SUBSTRATE, SEMICONDUCTOR SUBSTRATE, AND ELECTRONIC DEVICE
    • 用于制造半导体衬底的方法,用于形成半导体衬底的衬底,堆叠衬底,半导体衬底和电子器件
    • US20140183636A1
    • 2014-07-03
    • US14117158
    • 2012-06-26
    • Masahiro Mitani
    • Masahiro Mitani
    • H01L21/762H01L29/16H01L29/786
    • H01L21/76254H01L27/1266H01L29/16H01L29/78654
    • Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate. A method for manufacturing a SOI substrate (33) in which a plurality of SOI layers (15) are disposed on a base substrate (30) includes the steps of bonding a plurality of SOI wafers (10), in which an oxide film (14), a SOI layer (15), a BOX layer (12), and a Si support substrate (13) having a fragile layer (17) formed by ion irradiation in the inside and being made from a single crystal semiconductor material are stacked sequentially, to a base substrate (30) in such a way that the oxide film (14) is located on the side close to the base substrate (30), applying heat to the plurality of SOI wafers (10) to separate part of the Si support substrate (13) at the fragile layer (17) and transfer the oxide film (14), the SOI layer (15), the BOX layer (12), and a single crystal Si layer (18) which is part of the Si support substrate (13) to the base substrate (30), and subjecting the base substrate (30) to an etch back treatment to expose the BOX layer (12) by etching the transferred single crystal Si layer (18).
    • 在易碎层分离的多个单晶半导体膜中,可以防止膜厚变化,并将其转印到基底。 在基底(30)上设置多个SOI层(15)的SOI衬底(33)的制造方法包括将多个SOI晶片(10)接合的工序,其中,氧化膜(14) ),顺序地层叠具有通过离子照射在内部并由单晶半导体材料制成的脆性层(17)的SOI层(15),BOX层(12)和Si支撑基板(13) 以使得氧化膜(14)位于靠近基底(30)的一侧的方式施加到基底(30),向多个SOI晶片(10)施加热量以分离部分Si 在所述脆弱层(17)处的支撑基板(13),并且将所述氧化物膜(14),所述SOI层(15),所述BOX层(12)和作为所述Si的一部分的单晶Si层(18) 支撑基板(13)到基底基板(30),并且对基底基板(30)进行回蚀处理,以通过蚀刻转移的单个Cr来暴露BOX层(12) ystal Si层(18)。
    • 7. 发明申请
    • OVERHEAT PROTECTION CIRCUIT AND POWER SUPPLY INTEGRATED CIRCUIT
    • 超声波保护电路和电源集成电路
    • US20100321845A1
    • 2010-12-23
    • US12790070
    • 2010-05-28
    • Takashi ImuraTakao NakashimoMasakazu SugiuraAtsushi IgarashiMasahiro Mitani
    • Takashi ImuraTakao NakashimoMasakazu SugiuraAtsushi IgarashiMasahiro Mitani
    • H02H5/04
    • G05F1/569
    • Provided is a power supply integrated circuit including an overheat protection circuit with high detection accuracy. The overheat protection circuit includes: a current generation circuit including: a first metal oxide semiconductor (MOS) transistor including a gate terminal and a drain terminal that are connected to each other, the first MOS transistor operating in a weak inversion region; a second MOS transistor including a gate terminal connected to the gate terminal of the first MOS transistor, the second MOS transistor having the same conductivity type as the first MOS transistor and operating in a weak inversion region; and a first resistive element connected to a source terminal of the second MOS transistor; and a comparator for comparing a reference voltage having positive temperature characteristics and a temperature voltage having negative temperature characteristics, which are obtained based on a current generated by the current generation circuit.
    • 提供了一种具有高检测精度的过热保护电路的电源集成电路。 过热保护电路包括:电流产生电路,包括:第一金属氧化物半导体(MOS)晶体管,其包括彼此连接的栅极端子和漏极端子,所述第一MOS晶体管在弱反转区域中工作; 第二MOS晶体管,包括连接到第一MOS晶体管的栅极端子的栅极端子,第二MOS晶体管具有与第一MOS晶体管相同的导电类型并且在弱反转区域中操作; 以及连接到所述第二MOS晶体管的源极端子的第一电阻元件; 以及比较器,用于比较具有正温度特性的参考电压和具有负温度特性的温度电压,其基于由电流产生电路产生的电流获得。