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1. 发明授权

US06580126B1 Solid-state relay 失效
公开(公告)号：US06580126B1
公开(公告)日：2003-06-17
申请号：US09709582
申请日：2000-11-13
申请人： Masahiko Suzumura , Hitomichi Takano , Yuji Suzuki , Takashi Kishida , Yoshiki Hayasaki , Yoshifumi Shirai , Takeshi Yoshida , Yasunori Miyamoto
发明人： Masahiko Suzumura , Hitomichi Takano , Yuji Suzuki , Takashi Kishida , Yoshiki Hayasaki , Yoshifumi Shirai , Takeshi Yoshida , Yasunori Miyamoto
IPC分类号： H01L2976
CPC分类号： H01L29/7824 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/088 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48237 , H01L2224/48257 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.

2. 发明授权

US06373101B1 Solid-state relay 失效
标题翻译：固态继电器
公开(公告)号：US06373101B1
公开(公告)日：2002-04-16
申请号：US09709528
申请日：2000-11-13
申请人： Masahiko Suzumura , Hitomichi Takano , Yuji Suzuki , Takashi Kishida , Yoshiki Hayasaki , Yoshifumi Shirai , Takeshi Yoshida , Yasunori Miyamoto
发明人： Masahiko Suzumura , Hitomichi Takano , Yuji Suzuki , Takashi Kishida , Yoshiki Hayasaki , Yoshifumi Shirai , Takeshi Yoshida , Yasunori Miyamoto
IPC分类号： H01L2976
CPC分类号： H01L29/7824 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/088 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48237 , H01L2224/48257 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.
摘要翻译：由串联连接的LDMOSFET组成的固态继电器具有最小的输出电容。每个LDMOSFET被配置为具有第一导电类型的硅层，第一导电类型的漏极区域扩散在硅层的顶表面中，第二导电类型的阱区域在硅层中以横向间隔开地扩散与漏区域的关系以及在阱区域内扩散的第一导电类型的源极区域，以限定沿着硅层的顶表面在源极区域和阱区域的相对边缘之间延伸的沟道。每个LDMOSFET是由放置在支撑板上的硅衬底，硅衬底上的掩埋氧化物层和掩埋氧化物层上的硅层组成的SOI（绝缘体上硅）结构。阱区域在硅层的整个深度上扩散以使其底部与掩埋氧化物层接触，使得阱区域仅在邻近通道的小区域处与硅层形成P-N界面。由于这种减小的PN接口，并且由于掩埋氧化物层具有比硅层更低的电感性电容，因此可以大大减小漏 - 源电容，以使在非导电条件下继电器的输出电容最小化。

3. 发明授权

US06211551B1 Solid-state relay 失效
标题翻译：固态继电器
公开(公告)号：US06211551B1
公开(公告)日：2001-04-03
申请号：US09105464
申请日：1998-06-26
申请人： Masahiko Suzumura , Hitomichi Takano , Yuji Suzuki , Takashi Kishida , Yoshiki Hayasaki , Yoshifumi Shirai , Takeshi Yoshida , Yasunori Miyamoto
发明人： Masahiko Suzumura , Hitomichi Takano , Yuji Suzuki , Takashi Kishida , Yoshiki Hayasaki , Yoshifumi Shirai , Takeshi Yoshida , Yasunori Miyamoto
IPC分类号： H01L2976
CPC分类号： H01L29/7824 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/088 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48237 , H01L2224/48257 , H01L2224/49 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： A solid state relay composed of a series connected pair of LDMOSFETs has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting a much lower inductive capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.
摘要翻译：由串联连接的LDMOSFET组成的固态继电器具有最小的输出电容。每个LDMOSFET被配置为具有第一导电类型的硅层，第一导电类型的漏极区域扩散在硅层的顶表面中，第二导电类型的阱区域在硅层中以横向间隔开地扩散与漏区域的关系以及在阱区域内扩散的第一导电类型的源极区域，以限定沿着硅层的顶表面在源极区域和阱区域的相对边缘之间延伸的沟道。每个LDMOSFET是由放置在支撑板上的硅衬底，硅衬底上的掩埋氧化物层和掩埋氧化物层上的硅层组成的SOI（绝缘体上硅）结构。阱区域在硅层的整个深度上扩散以使其底部与掩埋氧化物层接触，使得阱区域仅在邻近通道的小区域处与硅层形成P-N界面。由于这种减小的PN接口，并且由于掩埋氧化物层具有比硅层更低的电感性电容，因此可以大大减小漏 - 源电容，以使在非导电条件下继电器的输出电容最小化。

4. 发明授权

US06448620B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06448620B2
公开(公告)日：2002-09-10
申请号：US09741812
申请日：2000-12-22
申请人： Yoshiki Hayasaki , Hitomichi Takano , Masahiko Suzumura , Yuji Suzuki , Yoshifumi Shirai , Takashi Kishida , Takeshi Yoshida , Takaaki Yoshihara
发明人： Yoshiki Hayasaki , Hitomichi Takano , Masahiko Suzumura , Yuji Suzuki , Yoshifumi Shirai , Takashi Kishida , Takeshi Yoshida , Takaaki Yoshihara
IPC分类号： H01L2701
CPC分类号： H01L29/7824 , H01L29/0878 , H01L29/66681 , H01L29/78624
摘要： To provide a semiconductor device having a large allowable current, a demanded withstand voltage, and small output capacitance and resistance, the semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, and the semiconductor layer includes a first conductivity type-drain region, a second conductivity type-well region apart from the drain region, a first conductivity type-source region in the well region apart from one end of the well region on the side of the drain region, a first conductivity type-drift region formed between one end of the well region and the drain region and in contact with the well region and the drain region, respectively, and a gate electrode formed spaced a gate oxide layer and on the well region located between the drift region and the source region; and the impurity concentration of the drift region decreases in the lateral direction and also in the vertical direction, respectively, as the distance from the drain region increases.
摘要翻译：为了提供具有大容许电流，所要求的耐受电压和小的输出电容和电阻的半导体器件，半导体器件包括形成在半导体衬底上的半导体层，并且半导体层包括第一导电类型 - 漏极区域，与漏极区分离的第二导电类型 - 阱区，在与漏极区一侧的阱区的一端分开的阱区中的第一导电型 - 源极区，形成在漏极区的一端和与阱区和漏极区分别接触的阱区和形成在栅极氧化物层之间以及位于漂移区和源极区之间的阱区上的栅极; 随着距离漏极区域的距离增加，漂移区域的杂质浓度分别在横向和垂直方向上减小。

5. 发明授权

US5780900A Thin film silicon-on-insulator transistor having an improved power dissipation, a high break down voltage, and a low on resistance 失效
标题翻译：具有改善的功率耗散，高分解电压和低导通电阻的薄膜绝缘体上硅晶体管
公开(公告)号：US5780900A
公开(公告)日：1998-07-14
申请号：US733164
申请日：1996-10-17
申请人： Yuji Suzuki , Hitomichi Takano , Masahiko Suzumura , Yoshiki Hayasaki , Takashi Kishida , Yoshifumi Shirai
发明人： Yuji Suzuki , Hitomichi Takano , Masahiko Suzumura , Yoshiki Hayasaki , Takashi Kishida , Yoshifumi Shirai
IPC分类号： H01L29/06 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/10
CPC分类号： H01L29/7824 , H01L29/0873 , H01L29/78624 , H01L29/0657 , H01L29/0878 , H01L29/402
摘要： A thin film transistor of SOI (Silicon-On-Insulator) type includes a buried oxide layer formed on a semiconductor substrate, a silicon layer of a first conductive type formed on the buried oxide layer, and an upper oxide layer formed on the silicon layer. The silicon layer has a body region of a second conductive type, source region of the first conductive type, drain region of the first conductive type, and a drift region of the first conductive type. The silicon layer is formed with a first portion of a thickness T1 in which the doping region is formed, and a second portion of a thickness T2 in which the body region is formed to reach the buried oxide layer. When the thicknesses T1 and T2 are determined so as to satisfy the relationships: 0.4 .mu.m
摘要翻译： SOI（绝缘体上硅）型薄膜晶体管包括在半导体衬底上形成的掩埋氧化物层，形成在掩埋氧化物层上的第一导电类型的硅层和形成在硅层上的上部氧化物层。硅层具有第二导电类型的主体区域，第一导电类型的源极区域，第一导电类型的漏极区域和第一导电类型的漂移区域。硅层形成有其中形成有掺杂区域的厚度T1的第一部分和形成有体区以到达掩埋氧化物层的厚度T2的第二部分。当厚度T1和T2被确定为满足以下关系：0.4μm

6. 发明授权

US08390173B2 MEMS switch and method of manufacturing the MEMS switch 失效
标题翻译： MEMS开关和制造MEMS开关的方法
公开(公告)号：US08390173B2
公开(公告)日：2013-03-05
申请号：US12935282
申请日：2009-03-30
申请人： Takaaki Yoshihara , Yoshiki Hayasaki , Takeo Shirai , Tomoaki Matsushima , Hiroshi Kawada , Yousuke Hagihara
发明人： Takaaki Yoshihara , Yoshiki Hayasaki , Takeo Shirai , Tomoaki Matsushima , Hiroshi Kawada , Yousuke Hagihara
IPC分类号： H01L41/00 , H02N1/00 , H02N11/00
CPC分类号： B81B3/0021 , B81B2201/032 , H01H59/0009 , H01H2057/006 , Y10T29/42
摘要： The MEMS switch comprises a substrate with signal-lines having fixed-contacts, a movable-plate with a movable-contact, a flexible support-member supporting the movable-plate, a static-actuator and a piezoelectric-actuator configured to contact the movable-contact with the fixed-contact. The movable-contact is provided at its longitudinal center with the movable-contact, and its both the longitudinal ends with static-movable-electrode-plate. The support-member is four strips disposed on portions outside of the both width ends of the movable plate. The strip extends along the longitudinal direction of the movable plate, provided with a first end fixed to the movable plate, and provided with a second end fixed to the substrate. The piezoelectric-element is disposed on an upper surface of the strip to be located at a portion outside of the width ends of the movable-plate. The piezoelectric-actuator is configured to develop the stress applied to the coupling-portion which is created between each the strip and the movable-plate.
摘要翻译： MEMS开关包括具有固定触点的信号线的基板，具有可移动触点的可移动板，支撑可移动板的柔性支撑构件，静电致动器和压电致动器，其构造成接触可动触点 - 与固定联系人联系。可动触点在其纵向中心处设置有可动触头，并且其两个纵向端部具有静电可动电极板。支撑构件是设置在可动板的两个宽度端的外侧的四个条。该条带沿可移动板的纵向方向延伸，设置有固定到可移动板的第一端，并设置有固定到基板的第二端。压电元件设置在条的上表面上，以位于可移动板的宽度端的外侧的部分。压电致动器被配置为产生施加到在每个条和可移动板之间产生的联接部分的应力。

7. 发明授权

US08098118B2 Bandpass filter and process of fabricating the same 失效
标题翻译：带通滤波器及其制造工艺
公开(公告)号：US08098118B2
公开(公告)日：2012-01-17
申请号：US12528070
申请日：2008-02-19
申请人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
发明人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
IPC分类号： H03H9/46 , H01P3/08
CPC分类号： H01P1/203 , H03H3/02 , H03H9/0542 , H03H9/542 , H03H9/564 , H03H9/568 , Y10T29/42
摘要： A bandpass filter includes a combination of a BAW filter and a patterned planar filter with stubs. The BAW filter is composed of a plurality of piezoelectric resonators to give a specific frequency bandpass, while the planer filter is configured to attenuate frequencies near and outside the bandpass. The resonators are connected in a ladder configuration between a first signal transmission path and a ground. The planar filter includes a strip line formed on a dielectric layer to define a second signal transmission path. The BAW filter and the planar filter are formed on a common substrate with the first and second transmission paths connected to each other. The BAW filter, in combination with the patterned planar filter added with the stub, can improve a deep near-band rejection inherent to the BAW filter, exhibiting an excellent out-of-band rejection over certain adjacent frequency ranges outside of the bandpass, and therefore give a sharp and wide bandpass.
摘要翻译：带通滤波器包括BAW滤波器和具有短截线的图案化平面滤波器的组合。 BAW滤波器由多个压电谐振器组成，以提供特定的频带通量，而平面滤波器被配置为衰减带通附近和外的频率。谐振器以第一信号传输路径和地之间的梯形结构连接。平面滤波器包括形成在电介质层上以限定第二信号传输路径的带状线。 BAW滤波器和平面滤波器形成在公共基板上，其中第一和第二传输路径彼此连接。 BAW滤波器与添加有短截线的图形平面滤波器组合可以改善BAW滤波器固有的深近带阻抗，在带通外的某些相邻频率范围内表现出优异的带外抑制，以及因此给出一个清晰而宽广的带通。

8. 发明申请

US20110024274A1 MEMS SWITCH AND METHOD OF MANUFACTURING THE MEMS SWITCH 失效
标题翻译： MEMS开关及制造MEMS开关的方法
公开(公告)号：US20110024274A1
公开(公告)日：2011-02-03
申请号：US12935282
申请日：2009-03-30
申请人： Takaaki Yoshihara , Yoshiki Hayasaki , Takeo Shirai , Tomoaki Matsushima , Hiroshi Kawada , Yousuke Hagihara
发明人： Takaaki Yoshihara , Yoshiki Hayasaki , Takeo Shirai , Tomoaki Matsushima , Hiroshi Kawada , Yousuke Hagihara
IPC分类号： H01H57/00 , H01L41/22
CPC分类号： B81B3/0021 , B81B2201/032 , H01H59/0009 , H01H2057/006 , Y10T29/42
摘要： The MEMS switch comprises a substrate with signal-lines having fixed-contacts, a movable-plate with a movable-contact, a flexible support-member supporting the movable-plate, a static-actuator and a piezoelectric-actuator configured to contact the movable-contact with the fixed-contact. The movable-contact is provided at its longitudinal center with the movable-contact, and its both the longitudinal ends with static-movable-electrode-plate. The support-member is four strips disposed on portions outside of the both width ends of the movable plate. The strip extends along the longitudinal direction of the movable plate, provided with a first end fixed to the movable plate, and provided with a second end fixed to the substrate. The piezoelectric-element is disposed on an upper surface of the strip to be located at a portion outside of the width ends of the movable-plate. The piezoelectric-actuator is configured to develop the stress applied to the coupling-portion which is created between each the strip and the movable-plate.
摘要翻译： MEMS开关包括具有固定触点的信号线的基板，具有可移动触点的可移动板，支撑可移动板的柔性支撑构件，静电致动器和压电致动器，其构造成接触可动触点 - 与固定联系人联系。可动触点在其纵向中心处设置有可动触头，并且其两个纵向端部具有静电可动电极板。支撑构件是设置在可动板的两个宽度端的外侧的四个条。该条带沿可移动板的纵向方向延伸，设置有固定到可移动板的第一端，并设置有固定到基板的第二端。压电元件设置在条的上表面上，以位于可移动板的宽度端的外侧的部分。压电致动器被配置为产生施加到在每个条和可移动板之间产生的联接部分的应力。

9. 发明申请

US20100117763A1 BANDPASS FILTER AND PROCESS OF FABRICATING THE SAME 失效
标题翻译： BANDPASS过滤器及其制造方法
公开(公告)号：US20100117763A1
公开(公告)日：2010-05-13
申请号：US12528070
申请日：2008-02-19
申请人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
发明人： Atsushi Suwa , Koji Sasabe , Futoshi Nishimura , Yoshiki Hayasaki , Tomoaki Matsushima , Sibei Xiong , Takaaki Yoshihara , Norihiro Yamauchi , Takeo Shirai
IPC分类号： H03H9/205 , H01P1/203 , H01L41/22
CPC分类号： H01P1/203 , H03H3/02 , H03H9/0542 , H03H9/542 , H03H9/564 , H03H9/568 , Y10T29/42
摘要： A bandpass filter includes a combination of a BAW filter and a patterned planar filter with stubs. The BAW filter is composed of a plurality of piezoelectric resonators to give a specific frequency bandpass, while the planer filter is configured to attenuate frequencies near and outside the bandpass. The resonators are connected in a ladder configuration between a first signal transmission path and a ground. The planar filter includes a strip line formed on a dielectric layer to define a second signal transmission path. The BAW filter and the planar filter are formed on a common substrate with the first and second transmission paths connected to each other. The BAW filter, in combination with the patterned planar filter added with the stub, can improve a deep near-band rejection inherent to the BAW filter, exhibiting an excellent out-of-band rejection over certain adjacent frequency ranges outside of the bandpass, and therefore give a sharp and wide bandpass.
摘要翻译：带通滤波器包括BAW滤波器和具有短截线的图案化平面滤波器的组合。 BAW滤波器由多个压电谐振器组成，以提供特定的频带通量，而平面滤波器被配置为衰减带通附近和外的频率。谐振器以第一信号传输路径和地之间的梯形结构连接。平面滤波器包括形成在电介质层上以限定第二信号传输路径的带状线。 BAW滤波器和平面滤波器形成在公共基板上，其中第一和第二传输路径彼此连接。 BAW滤波器与添加有短截线的图形平面滤波器组合可以改善BAW滤波器固有的深近带阻抗，在带通外的某些相邻频率范围内表现出优异的带外抑制，以及因此给出一个清晰而宽广的带通。

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