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1. 发明授权

US08451350B2 Solid-state imaging device, camera module, and imaging method 失效
标题翻译：固态成像装置，相机模块和成像方法
公开(公告)号：US08451350B2
公开(公告)日：2013-05-28
申请号：US13049334
申请日：2011-03-16
申请人： Masahiko Nozaki , Takeshi Nakano , Junichi Hosokawa
发明人： Masahiko Nozaki , Takeshi Nakano , Junichi Hosokawa
IPC分类号： H04N9/64
CPC分类号： H04N5/361
摘要： According to one embodiment, a third optical black portion is arranged in parallel with a first optical black portion in a row direction and in parallel with a second optical black portion in column direction. At least one of the vertical line correction circuit and the horizontal line correction circuit adds/subtracts arithmetic average of the third black level signal generated by the third optical black portion.
摘要翻译：根据一个实施例，第三光学黑色部分与行方向上的第一光学黑色部分平行布置，并且与列方向上的第二光学黑色部分平行布置。垂直线校正电路和水平线校正电路中的至少一个对由第三光学黑色部分产生的第三黑电平信号的算术平均值进行加/减。

2. 发明授权

US08537254B2 Image signal processing device and solid-state imaging device 失效
标题翻译：图像信号处理装置和固态成像装置
公开(公告)号：US08537254B2
公开(公告)日：2013-09-17
申请号：US13232219
申请日：2011-09-14
申请人： Yuji Miyashita , Junichi Hosokawa , Masahiko Nozaki
发明人： Yuji Miyashita , Junichi Hosokawa , Masahiko Nozaki
IPC分类号： H04N5/20
CPC分类号： H04N5/185 , H04N5/361
摘要： According to the embodiment, a feedback clamp circuit is included, which increases or decreases a clamp parameter so that a black level approaches a target value while controlling a change amount of the clamp parameter, which sets the black level, based on the black level read out from OB pixels.
摘要翻译：根据实施例，包括反馈钳位电路，其增加或减少钳位参数，使得黑电平接近目标值，同时基于黑电平读取来控制设置黑电平的钳位参数的变化量从OB像素出来。

3. 发明授权

US5847432A Semiconductor device and production method therefor 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5847432A
公开(公告)日：1998-12-08
申请号：US457724
申请日：1995-06-01
申请人： Masahiko Nozaki
发明人： Masahiko Nozaki
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L29/76 , H01L21/265
CPC分类号： H01L21/823807 , H01L27/0922 , Y10S438/981
摘要： A semiconductor device to which two kinds of electric voltage can be supplied comprises: a first MOS transistor formed in the first well having a first conduction type and being fixed to a first electric potential, a second MOS transistor formed in a second well having a second conduction type different from the first one and being fixed to a second electric potential higher than the first electric potential, and a third well formed between the first and second wells having the second conduction type and being fixed to a ground electric potential. The first MOS transistor comprises a first gate oxide film having a prescribed thickness and a first gate electrode having a prescribed gate length, while the second MOS transistor comprises a second gate oxide film having a thickness larger than the prescribed thickness of the first gate oxide film and a second gate electrode having a gate length longer than the prescribed thickness of the first gate length.
摘要翻译：可以提供两种电压的半导体器件包括：形成在具有第一导电类型并固定到第一电位的第一阱中的第一MOS晶体管，形成在具有第二阱的第二阱中的第二MOS晶体管导电类型不同于第一电极并被固定到高于第一电位的第二电位，以及形成在具有第二导电类型并被固定为接地电位的第一阱和第二阱之间的第三阱。第一MOS晶体管包括具有规定厚度的第一栅极氧化膜和具有规定栅极长度的第一栅极电极，而第二MOS晶体管包括厚度大于第一栅极氧化膜的规定厚度的第二栅极氧化膜以及具有比第一栅极长度的规定厚度长的栅极长度的第二栅极电极。

4. 发明授权

US5502337A Semiconductor device structure including multiple interconnection layers with interlayer insulating films 失效
标题翻译：半导体器件结构包括具有层间绝缘膜的多个互连层
公开(公告)号：US5502337A
公开(公告)日：1996-03-26
申请号：US344572
申请日：1994-11-18
申请人： Masahiko Nozaki
发明人： Masahiko Nozaki
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/485 , H01L23/528 , H01L23/48
CPC分类号： H01L24/05 , H01L23/5283 , H01L24/48 , H01L2224/04042 , H01L2224/05009 , H01L2224/05093 , H01L2224/05095 , H01L2224/05558 , H01L2224/05599 , H01L2224/48247 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/181
摘要： The present invention relates to a bonding pad electrode structure having sufficiently large allowable current and improved to prevent generation of cracks in an interlayer insulating film by mechanical stress at the time of wire bonding. Interlayer insulating films are provided directly on a semiconductor substrate. An uppermost interconnection layer is provided on interlayer insulating films. Since a lower interconnection layer does not exist immediately below a portion of the uppermost interconnection layer used as a bonding pad, cracks are not generated in the interlayer insulating films at the time of wire bonding. Further, since the uppermost interconnection layer is connected to lower interconnection layers, the current entering the bonding pad is dispersed to these interconnection layers.
摘要翻译：本发明涉及具有足够大的容许电流并且改进的焊盘电极结构，以防止在引线接合时机械应力产生层间绝缘膜中的裂纹。层间绝缘膜直接设置在半导体基板上。在层间绝缘膜上设置最上层的互连层。由于在用作接合焊盘的最上部互连层的一部分之下不存在下部互连层，因此在引线接合时在层间绝缘膜中不产生裂纹。此外，由于最上层的布线层连接到下互连层，所以进入焊盘的电流分散到这些互连层。

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